Temperature sensing unit switch clock circuit capable of eliminating mismatch influence and control method thereof

Abstract

The invention discloses a temperature sensing unit switch clock circuit capable of eliminating mismatch influence and a control method thereof, and relates to the integrated circuit technology; the temperature sensing unit switch clock circuit comprises a current mirror group formed by N current sources in parallel, a current source switching circuit, a triode group and an output unit, a first control unit is provided with N output ends which are connected with control ends of N current mirror input selection switches in a one-to-one correspondence manner; the control ends of a triode input selection switch and a triode output selection switch are connected to a second control unit, and N is an integer greater than 7; the first control unit comprises a trigger level width control module and is used for outputting a square wave signal with a pulse width a to each output end of the first control unit; the second control unit comprises a periodic square wave generation circuit with a dutyratio of 50%; the temperature sensing unit switch clock circuit is characterized in that the periodic square wave generating circuit comprises a square wave period setting circuit which is used for setting a period value b of a periodic square wave, and b is equal to a. According to the invention, the mismatch degree can be greatly reduced.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] In the ΔVBE circuit generated by the temperature sensing circuit, DEM technology and chopping technology can be used to eliminate the influence of current mirror mismatch and pnp mismatch. Such as figure 1 shown. The principle is that the DEM clock CKD<15:0> / CKDN<15:0> and the chopping clock CKC / CKCN are independent of each other or there is no specific design relationship between them (where CKD<15:0> and CKDN<15: 0> The phase difference is 180°, and the phase difference between CKC and CKCN is also 180°), for example, the clock period of CKD<15:0> / CKDN<15:0> is 16T, and the high level time is T. The clock cycle of CKC / CKCN is 2T. [0003] After using the DEM technology and the chopping technology, although the purpose of reducing the current mirror mismatch error and the PNP mismatch error can be achieved, if the relat...

AI Technical Summary

Problems solved by technology

[0003] After using DEM technology and chopping technology, although the purpose of reducing the current mirror mismatch error and PNP mismatch error can be achieved, if the relevant clock circuit is not properly set, the best effect cannot be achieved.

[0004] If the chopping clock period is set too small, chopping will be too frequent, which will bring adverse effects such as clock feedthrough and power consumption increase; if the chopping clock period is set too large, each current mirror can only flow in A PNP tube, if the mismatch of the PNP tube is serious, the final chopping effect will be greatly reduced

Images