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FPGA-based Join algorithm implementation method, system and device and medium

An implementation method and system implementation technology, which is applied in the field of FPGA data processing, can solve the problems of low data processing efficiency in databases, achieve the effect of improving throughput, improving efficiency, and realizing data processing

Pending Publication Date: 2020-12-11
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of this, the purpose of the embodiment of the present invention is to propose an FPGA-based Join algorithm implementation method, system, device and medium to solve the problem of low data processing efficiency in databases in the prior art

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  • FPGA-based Join algorithm implementation method, system and device and medium
  • FPGA-based Join algorithm implementation method, system and device and medium

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Embodiment Construction

[0027] In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0028] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are to distinguish two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present invention. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a process, method, system, product or other steps or elements inherent in a process, method, system, product, or device comprising a series of steps or elements.

[0029] ...

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Abstract

The invention provides an FPGA-based Join algorithm implementation method, system and device and a medium. The method comprises the following steps of receiving and storing small table data; receivingand temporarily storing big table data; dividing the big table data into multiple paths, and performing FIFO processing on all paths of big table data in parallel; sequentially judging whether each path of big table data is matched with each path of small table data or not; and outputting the large table data and the small table data which match each other. The big table data is divided into multiple paths, so that the big table data can be reasonably distributed, the data is effectively managed, and the data processing efficiency of the database is improved; by performing FIFO processing onall paths of big table data in parallel, the response time in the data processing process can be shortened, and compared with a single-process data processing mode, the task waiting time can be shortened, the data reading throughput rate can be increased, rapid and effective data processing can be realized, and the data matching efficiency can be improved.

Description

technical field [0001] The present invention relates to the technical field of FPGA data processing, in particular to an FPGA-based Join algorithm implementation method, system, device and medium. Background technique [0002] In the current semiconductor process, system power consumption has become the main obstacle to further increase the main frequency of the CPU. At the same time, due to the characteristics of the instruction set of the CPU, the data processing capability of the large database has encountered a bottleneck. When the amount of data sent by the database is large, the data needs to be relocated to the FPGA for processing. FPGA is a product of further development on the basis of programmable devices such as PAL and GAL. It appears as a semi-custom circuit in the field of application-specific integrated circuits. It not only solves the shortcomings of custom circuits, but also overcomes the original programmable Due to the limited number of device gates, it i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/2455G06F16/22G06F16/2453
CPCG06F16/2456G06F16/2255G06F16/24532
Inventor 牛晓威张明瑞王培培王文盛
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD