FPGA layout legalization method based on maximum flow algorithm

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) layout legalization method based on a maximum flow algorithm, and relates to the technical field of FPGAs (Field Programmable Gate Array). The method comprises the following steps of abstracting the initial layout state to establish a residual graph, assigning values to directed edges formed by abstracting the relationship between theillegal nodes and the vacant positions in the residual graph by utilizing the line length to serve as the expenditure of the edges, and solving the residual graph based on a minimum expenditure maximum flow algorithm to obtain legal positions of the illegal nodes, and placing each illegal node to a corresponding legal position to complete layout legalization. The maximum flow algorithm is appliedto the legalization part of the quadratic linear programming algorithm, so that the legalization process which does not have guidance originally becomes guidance, the quality of the final solution isimproved to a certain extent, and the legalized line length is shorter and the layout result is better.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a method for legalizing FPGA layout based on a maximum flow algorithm. Background technique [0002] Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) is a chip widely used in household appliances, large machinery and even aerospace. The use of FPGA chips is inseparable from electronic design automation (Electronic Design Automation, EDA) tools. Layout is an important part of the EDA tool, which has a great impact on the running speed of the EDA tool itself and the final quality of the processed circuit. [0003] In recent years, the circuit scale of FPGA chips has grown rapidly, making its functions more powerful, but it has also brought challenges to the corresponding EDA tools. Analytical algorithms have become one of the mainstream directions of today's layout algorithms because they can use mathematical methods to quickly obtain the global optimal solution....

AI Technical Summary

Problems solved by technology

The quadratic linear programming algorithm is a kind of analytical algorithm. When it is specifically applied to solve the layout problem, it shows the characteristics of fast solution. However, after the solution is completed, there are still illegal layouts, such as the common overlapping node, so it needs to be legalized again

Although this method is simple and easy to implement, it does not have any guidance, and there are also the following problems in the selection, for example: if the location distance is marked by the Manhattan distance, can the location with the closest distance be better than the location with a long distance? There are multiple locations with the same Manhattan distance. Do these locations have the same advantages and disadvantages? These problems lead to the fact that although the original legalization process can quickly legalize the illegal layout, it cannot take into account the quality of the legalized layout, which often leads to unsatisfactory final solutions.

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