VMAC high-speed address learning method and electronic equipment

Abstract

The invention discloses a VMAC high-speed address learning method, provides a structure for controlling Cache, data Cache and Main memory in order to improve the VMAC address learning speed and realize VMAC address learning high-speed pipeline processing, and provides a refreshing mechanism for controlling Cache so as to reduce the data error processing rate caused by high-speed processing. High-speed pipeline processing and redundant operation combination of VMAC address learning are realized, the access effectiveness is improved, the data consistency is ensured, and the VMAC address learningspeed is increased. According to the method, the influence of the Min memory read-write delay on the system design can be reduced, and the delay of obtaining the latest data can be reduced by the 'data Cache'; the influence of the working frequency on the system design can be reduced, the working frequency is improved, and in order to meet the time sequence requirement, the number of stages of the stored data is increased from reading to writing, and the data Cache can merge the temporary state of the writing operation. The invention further provides corresponding electronic equipment.

Description

technical field [0001] The invention belongs to the technical field of IP (Internal Protocol, network protocol) communication, and more specifically, relates to a VMAC high-speed address learning method and electronic equipment. Background technique [0002] The VMAC function belongs to the MAC (Media Access Control, Media Access Control) address security function. In the current IP access network based on Layer 2 Ethernet forwarding as the core, the untrustworthy MAC address of end users may cause MAC address spoofing. In the uplink direction, when the access device receives the message sent by the user side, it will convert the "untrusted" terminal user source MAC address into a "trusted" VMAC (Virtual Media Access Control, virtual media access control) address, And learn the VMAC address, and then forward it to the upper network. In the downlink direction, when a packet received from the network side is sent to the user port, the address learning table is queried, and t...

AI Technical Summary

Problems solved by technology

Since the update logic of the V-State state table is serial, that is, after the application of the previous data message is processed, it is not known whether the application of the next data message reaches the VMAC application threshold, which limits the speed of VMAC address learning. Update of the V-State status table

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