Electronic package and a manufacturing method therefor

Abstract

An electronic package and a manufacturing method therefor, the electronic component is arranged on a carrier in a flip-chip manner, the electronic component is coated with the encapsulation layer, andpart of the material of the encapsulation layer, part of the material of the electronic component and part of the material of the carrier are removed through a leveling operation so as to reduce theoverall thickness of the electronic package.

Description

technical field [0001] The invention relates to a semiconductor packaging process, in particular to an electronic package and its manufacturing method. Background technique [0002] At present, there are many technologies applied in the field of chip packaging, such as Chip Scale Package (CSP for short), Direct Chip Attached (DCA for short) or Multi-Chip Module (MCM for short). ) and other flip-chip packaging processes, or integrate the three-dimensional stacking of chips into a three-dimensional integrated circuit (3D IC) chip stacking process. [0003] Such as figure 1 As shown, it is known that a quad flat no leads (QFN) type semiconductor package 1 is known, and the semiconductor chip 11 is flip-chip connected to a lead frame 10 via a plurality of solder bumps 110 , and then coat the semiconductor chip 11, the lead frame 10 and the solder bump 110 with the encapsulant 12, and then cut, so that the sides (Side Surface) and bottom surface (Bottom Surface) of each guide p...

AI Technical Summary

Problems solved by technology

[0005] However, under the requirement of multi-contact (I / O) quantity and tiny package volume, especially the overall thickness t of the semiconductor package 1 is less than 0.3 mm, the required thickness d of the semiconductor chip 11 is extremely small, so when When the semiconductor chip 11 is connected to the lead frame 10, it is easy to be crushed and cracked, resulting in poor reliability of the semiconductor package 1.

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