Chip packaging structure, preparation method thereof, and packaged chip
A chip packaging structure and chip packaging technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problem that the overall package thickness of the ball grid array package is thick, the grid array package has poor solderability, and it is difficult to meet the packaging requirements. It can meet the requirements of package reliability, meet the requirements of light and thin, and improve the solderability of the package.
Pending Publication Date: 2021-01-05
SHANGHAI AWINIC TECH CO LTD
View PDF0 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0003] Existing packaging structures mainly include Land Grid Array (LGA) and Ball Grid Array (BGA), but in practical applications, these two packaging structures have different problems. The overall package thickness of the Shan array package is relatively thick, which is difficult to meet the requirements of light and thin packages, while the package of the grid array package has poor solderability
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
preparation example Construction
[0067] Correspondingly, the embodiment of the present application also provides a method for preparing a chip packaging structure, such as Figure 10 shown, including:
[0068] S101: Provide a substrate, the substrate includes a first surface and a second surface arranged opposite to each other, the substrate further includes interconnection wiring, the interconnection wiring is located inside the substrate, and the first surface is used for setting all The chip is electrically connected to the interconnection wire;
[0069] S102: forming a bottom pad, where the bottom pad is located on the second surface of the substrate and is electrically connected to the interconnection wiring;
[0070] S103: forming bump pads, the plurality of bump pads correspond to the plurality of bottom pads one by one, the bump pads are arranged on the surface of the bottom pad corresponding to the bump pads, And the surface of the bump pad away from the substrate is higher than the second surface....
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention discloses a chip packaging structure, a preparation method thereof, and a packaged chip. According to the chip packaging structure, a convex spot welding pad is arranged on the surface of a bottom welding pad; the surface of one side, far away from a substrate, of the convex spot welding pad, is higher than the second surface of the substrate, that is, the bottom surface of the convex spot welding pad protrudes outwards relative to the bottom surface of the substrate, so that the probability of abnormal welding of the packaging structure during SMT welding can be reduced, and thepackaging reliability requirement of the packaging structure can be met; meanwhile, the height of the convex spot welding pad can be smaller than that of a solder ball structure, so that the overallthickness of the packaging structure can be ensured to be smaller, and the lightening and thinning requirements of the packaging structure can be met.
Description
technical field [0001] The present application relates to the technical field of semiconductors, and more specifically, relates to a chip packaging structure, a manufacturing method thereof, and a packaged chip. Background technique [0002] With the continuous upgrading of consumer electronics technology in the market, electronic devices such as mobile phones, smart wearable devices and tablet computers have higher and higher requirements for the reliability of chip (Integrated Circuit Chip) packaging. [0003] The existing packaging structures mainly include Land Grid Array Package (LGA) and Ball Grid Array Package (BGA). However, in practical applications, these two packaging structures have different problems. The overall package thickness of the Shan array package is relatively thick, and it is difficult to meet the requirements of thinner and lighter packages, while the package of the grid array package has poor solderability. How to obtain a packaging structure that ...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More IPC IPC(8): H01L23/498H01L21/48
CPCH01L21/4846H01L21/4853H01L23/49816H01L23/49838H01L2224/16225H01L2224/17H01L2924/181H01L2924/00012
Inventor 姜域
Owner SHANGHAI AWINIC TECH CO LTD