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Method of manufacturing thin semiconductor chip using dummy sidewall layer and device thereof

A semiconductor and sacrificial layer technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as chip size and thickness cannot be satisfied

Pending Publication Date: 2021-01-19
STMICROELECTRONICS (ROUSSET) SAS +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Due to the limitations of conventional IC chips, the size and thickness of the chips cannot meet the growing demand of the industry to provide IC chips with the smallest size

Method used

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  • Method of manufacturing thin semiconductor chip using dummy sidewall layer and device thereof
  • Method of manufacturing thin semiconductor chip using dummy sidewall layer and device thereof
  • Method of manufacturing thin semiconductor chip using dummy sidewall layer and device thereof

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Embodiment Construction

[0029] In the ensuing description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, one skilled in the relevant art will appreciate that the embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, and the like. In other instances, well-known structures associated with semiconductor chips or semiconductor chip packages have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0030] Unless the context requires otherwise, throughout the following specification and claims the word "comprise" and variations thereof, such as "comprises" and "comprising" are to be interpreted in an open, inclusive sense , that is, "including, but not limited to". Additionally, the terms "first", "second" and similar sequence designations are to be interpreted as being interchangeable unless the con...

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Abstract

The invention relates to a method of manufacturing a thin semiconductor chip using a dummy sidewall layer and a device thereof. The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip ismounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 [mu]m in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible / rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

Description

technical field [0001] The present disclosure relates to a method of manufacturing an integrated circuit (IC) chip with reduced thickness and an apparatus thereof, suitable for being applied to wearable electronic devices and flexible devices. Background technique [0002] With growing interest in flexible devices and wearable electronic devices, the semiconductor manufacturing industry is struggling to find a manufacturing method to thin semiconductor devices or IC chips to ultra-thin levels. The state of the art in existing semiconductor manufacturing processes typically produces IC chips having a thickness greater than about 100 μm, or thicker. However, further thinning of IC chips is not feasible due to inherent limitations of existing fabrication processes. [0003] With the limited ability to thin the IC chip thickness, the semiconductor industry cannot expand its IC chip application to various technical fields, such as rollable displays, foldable mobile devices, wear...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L23/31H01L21/50H01L21/56
CPCH01L21/50H01L21/568H01L23/3185H01L23/488H01L2224/16225H01L2224/32225H01L2224/73204H01L2924/00
Inventor L·埃拉尔D·帕克D·加尼
Owner STMICROELECTRONICS (ROUSSET) SAS
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