Lead bonding method for system-on-package chip
A wire bonding and system packaging technology, applied in the manufacturing of electrical components, electrical solid state devices, semiconductor/solid state devices, etc., can solve problems such as functional failure, reduced reliability of chip packaging, bonding and other process pollution, and achieve high performance. Reference value, easy to be polluted, high package reliability effect
Pending Publication Date: 2021-01-22
TIANJIN JINHANG COMP TECH RES INST
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Problems solved by technology
However, in order to save costs, the packaging at this stage uses copper wires for bonding and cannot strictly control the packaging environment, which can easily cause contamination in bonding and other processes, resulting in a significant reduction in the reliability of chip packaging, and even functional failure.
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[0028] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
[0029] The system packaging chip wire bonding method of the present invention comprises the following steps:
[0030] S1: Determine the bonding welding process
[0031] There are two types of wire bonding: ball bonding and wedge bonding.
[0032] The basic steps include: forming a first solder joint on the chip surface, forming a line arc, and finally forming a second solder joint on the chip substrate. The difference between the two types of bonding is that ball bonding forms a solder ball at the beginning of each cycle, and then solders the solder ball to the chip substrate to form the first solder joint; Next, use a wedge-shaped rivet for direct welding.
[0033] During the failure analysis of the failed samples,...
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The invention discloses a lead bonding method for a system-on-package chip. The lead bonding method comprises the following steps: S1, determination of a bonding welding process: forming a first welding spot on the surface of the chip, forming a wire arc, and finally forming a second welding spot on a chip substrate; S2, selection of a bonding mode: conducting welding is in a thermal ultrasonic bonding mode; and S3, improvement and reinforcement of a lead material: selecting a palladium-plated copper wire as a lead, coating the surface of the copper wire with a layer of metal palladium throughan electroplating method, and enabling the metal palladium to cover the periphery of the copper wire. The method is high in packaging reliability, solves the problem that the chip is easy to pollute,and has a very high reference value in the field of packaging engineering.
Description
technical field [0001] The invention belongs to the technical field of key technology of system packaging chips, and relates to a wire bonding method of system packaging chips. Background technique [0002] With the continuous shrinking of integrated circuits and the exponential growth of integration, the reliability test and failure analysis of system-in-package chips have gradually become a very important link. As we all know, the system package chip is formed by packaging and integrating various power devices, active and passive devices, so its performance and quality not only depend on the pros and cons of the electronic components used, but also are closely related to the entire packaging process. Therefore, how to use advanced detection methods and micro-analysis technology to quickly determine the failure location and mode of the failed chip, and provide effective and timely feedback on reliability improvement and improvement of reinforcement measures has become a hot...
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IPC IPC(8): H01L21/60H01L23/498
CPCH01L24/85H01L23/49866H01L2224/85205H01L2224/85801H01L2224/48465H01L2224/85181H01L2224/78301
Inventor 徐艺轩朱天成张楠候俊马
Owner TIANJIN JINHANG COMP TECH RES INST