Grid node encoding method and system based on integrated circuit impedance network extraction

Abstract

The invention relates to a grid node encoding method and system based on integrated circuit impedance network extraction. The method comprises the following steps: carrying out mesh generation on a multi-layer integrated circuit layout to obtain triangular meshes; sequentially carrying out continuous encoding on ports in the triangular grid; obtaining a distance from a grid node to a port in the triangular grid; encoding the corresponding grid nodes according to the distances from the grid nodes in the triangular grid to the ports; listing and writing a finite element equation set for calculating the potential field of the integrated circuit according to the information of the grid nodes on the coded triangular grid to obtain a finite element sparse matrix; according to the codes of the grid nodes of the finite element grid, eliminating the non-port grid nodes of the finite element sparse matrix by repeatedly utilizing triangular star transformation to obtain a multi-port network admittance matrix; and extracting an impedance network model according to the multi-port network admittance matrix. The sequential elimination method provided by the invention improves the extraction accuracy of the impedance network model of the multi-layer super-large-scale integrated circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a grid node coding method and system based on integrated circuit impedance network extraction. Background technique [0002] The extraction of multi-layer VLSI impedance network model is an important task in the back-end verification of integrated circuits. The conventional extraction method is to calculate the S-parameter matrix of VLSI using the simplified transmission line method or field-based calculation method, and then based on The S-parameter matrix is ​​converted to an impedance network model. The calculation speed of the transmission line method is fast, but due to the large approximation of the layout of the integrated circuit, the calculation results of the simple and regular layout in the early stage of processing are accurate, but in recent years, the structure has become more and more complex, and the scale ranges from centimeters to centimeters. Nanoscale layou...

AI Technical Summary

Problems solved by technology

However, in the process of elimination, the elimination order of internal nodes will affect the accuracy of the finally obtained multi-port network impedance matrix. Improper elimination order of internal nodes may cause inaccurate calculation results, and the impedance network model cannot be effectively extracted.

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