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Chip reset method and system, storage medium and electronic equipment

A reset method and chip technology, applied in the computer field, can solve problems such as program hangs and abnormal operation of digital circuits.

Pending Publication Date: 2021-02-23
GREE ELECTRIC APPLIANCES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But at this time, the power supply voltage continues to drop, and the core voltage of the chip also drops slowly. When the core voltage of the chip drops to a certain level, the digital circuit of the chip will work abnormally, causing the program to hang up.

Method used

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  • Chip reset method and system, storage medium and electronic equipment
  • Chip reset method and system, storage medium and electronic equipment
  • Chip reset method and system, storage medium and electronic equipment

Examples

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Embodiment 1

[0024] According to an embodiment of the present invention, a chip reset method is provided, figure 1 It shows a schematic flowchart of a chip reset method proposed in Embodiment 1 of the present invention, as shown in figure 1 As shown, the chip reset method may include: Step 110 to Step 130 .

[0025] In step 110, it is detected whether the LVD module in the chip generates an LVD reset signal.

[0026] Here, by detecting whether the LVD reset signal is detected, it can be judged whether the chip is faulty. The LVD module is a module used to detect the power supply voltage of the chip inside the chip. When the LVD module detects that the power supply voltage of the chip has dropped from the normal voltage to the set value, it will generate a reset signal to the chip to reset the chip. For example, the power supply voltage of the chip is 5V, and the voltage triggering the LVD reset signal is 4.1V, then the LVD module generates the LVD reset signal when the working voltage of...

Embodiment 2

[0035] On the basis of the above embodiments, another embodiment of the present invention also provides a chip reset method, figure 2 It shows a schematic flowchart of a chip reset method proposed in Embodiment 2 of the present invention, as shown in figure 2 As shown, the chip reset method may include: Step 210 to Step 230 .

[0036] In step 210, it is detected whether the LVD module in the chip generates an LVD reset signal.

[0037] Here, by detecting whether the LVD reset signal is detected, it can be judged whether the chip is faulty. The LVD module is a module used to detect the power supply voltage of the chip inside the chip. When the LVD module detects that the power supply voltage of the chip has dropped from the normal voltage to the set value, it will generate a reset signal to the chip to reset the chip. For example, the power supply voltage of the chip is 5V, and the voltage triggering the LVD reset signal is 4.1V, then the LVD module generates the LVD reset ...

Embodiment 3

[0058] According to an embodiment of the present invention, a chip reset system corresponding to a chip reset method is also provided. see Figure 4 A schematic structural diagram of a chip reset system proposed by an embodiment of the present invention is shown. A chip reset system, comprising:

[0059] The detection module is used to detect the LVD reset signal generated by the LVD module in the chip;

[0060] A control module, configured to enable the watchdog and suspend the central processing unit of the chip after the LVD reset signal ends;

[0061] The control module is further configured to control the watchdog to send a chip reset signal to reset the chip after the watchdog timer ends.

[0062] Optionally, the timing time of the watchdog is not less than the time for the chip to fall from a preset voltage value capable of triggering the LVD reset signal to a completely power-down state.

[0063] Optionally, if the detection module does not detect the LVD reset sig...

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PUM

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Abstract

The invention discloses a chip reset method and system, a storage medium and electronic equipment, and relates to the technical field of computers. The method comprises the steps that whether an LVD module in a chip generates an LVD reset signal or not is detected; if the LVD reset signal is detected, enabling a watchdog after the LVD reset signal is ended, and suspending a central processing unitof the chip; and after the timing of the watchdog is finished, controlling the watchdog to send a chip reset signal so as to reset the chip. The method has the beneficial effects that the central processing unit can be suspended when the power supply voltage of the chip is unstable, so that the condition that a program running in the chip is suspended due to the unstable voltage is avoided.

Description

technical field [0001] The invention belongs to the technical field of computers, and in particular relates to a chip reset method, system, storage medium and electronic equipment. Background technique [0002] In the prior art, when the LVD (Low Voltage Detection) detects that the power supply voltage of the chip is lower than the set value, the LVD will generate a reset signal to the chip, thereby urging the chip to reset. [0003] However, in practical applications, because many products use capacitors with large capacitance values, the power supply voltage of the chip drops very slowly. At this time, when the LVD detects that the power supply voltage is lower than the set value, it will prompt the chip to reset and make the program run again. But at this time, the power supply voltage continues to drop, and the core voltage of the chip also drops slowly. When the core voltage of the chip drops to a certain level, the digital circuit of the chip will work abnormally, cau...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/24G06F11/07
CPCG06F1/24G06F11/0757
Inventor 吴建文
Owner GREE ELECTRIC APPLIANCES INC
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