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Method and device for reducing network-on-chip power consumption, CPU chip and server

An on-chip network and power consumption technology, applied in the computer field, can solve the problem of not being able to adjust the working frequency adaptively

Active Publication Date: 2021-02-23
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This type of frequency conversion technology can optimize the energy consumption ratio of SOC to a certain extent, but since the entire NoC runs at a uniform operating frequency and cannot adaptively adjust the operating frequency, there is still a lot of room for improvement and improvement

Method used

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  • Method and device for reducing network-on-chip power consumption, CPU chip and server

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Embodiment Construction

[0067] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0068] It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0069] On the one hand, the embodiment of the present invention provides a method for reducing the power consumption of the network on chip, such as figure 2 As shown, the method of this embodiment may include:

[0070] Step 101: Dividing the network on chip NoC into two or more non-overlapping areas, and each area uses an independent working clock;

[0071] Since the devices mounted on each NIU are different, each device has different requirements for NoC bandwidth in different time ranges. Therefore, the NoC can ...

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Abstract

The embodiment of the invention discloses a method and device for reducing network-on-chip power consumption, a CPU chip and a server, relates to the technical field of computers, and can effectivelyreduce the network-on-chip power consumption. The method comprises the following steps: dividing a network-on-chip (NoC) into more than two regions which are not overlapped with each other, wherein each region uses an independent working clock; acquiring working state data of a routing unit RU of the NoC; calculating the expected working frequency of each region of the NoC according to the workingstate data; and adjusting the working frequency of each region of the NoC to the expected working frequency. The invention is suitable for occasions of reducing network-on-chip power consumption.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a method, device, CPU chip and server for reducing power consumption of an on-chip network. Background technique [0002] With the development of integrated circuits and the improvement of technology, the integration level of chips is constantly improving, and large-scale SOC (System on Chip, system-on-chip) design has become the mainstream. NoC (Network on Chip, network on chip) is used to realize the on-chip interconnection of various devices in the SOC, mainly including multiple network interface units (Network Interface Unit, NIU) and routing units (Router Unit, RU), such as figure 1 As shown, NIUs are at the boundary of the NoC, and each NIU is used to connect to a mounted device, and is responsible for managing all requests sent by the device and all requests sent to the device. For each request sent by the device, the NIU will record the relevant information and forward...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/324G06F1/3206G06F15/78
CPCG06F1/324G06F1/3206G06F15/7807Y02D10/00
Inventor 徐祥俊黄维王明波
Owner HYGON INFORMATION TECH CO LTD
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