Implementation method of pipeline pre-branching

Abstract

The invention relates to an implementation method of pipeline pre-branching. According to the implementation method of pipeline pre-branching, for a processor core, the complexity of a pipeline usually determines the performance of a core instruction set architecture, and even determines a market area suitable for a processor. In fact, the implementation complexity of assembly line hardware is notdecided by an instruction set, but aiming at different market areas, kernel assembly lines with different complexity degrees are needed, and then a corresponding instruction set architecture is provided. Therefore, the viewpoint that any one of the RISC and the CISC can replace the other one is unscientific unless the related application market disappears. The circuit structure of the short assembly line is easier to obtain the low-end processor market, and the complex ultra-long assembly line is more suitable for the high-end processor market. However, the hardware structure of the ultra-long assembly line can bring a very troublesome pre-branching problem, and the technical scheme of the invention can better solve the pre-branching problem for the structure of the ultra-long assembly line, so that the structure of the ultra-long assembly line has higher efficiency.

Description

technical field [0001] The invention relates to the field of integrated circuits and computers, in particular to a method for realizing pipeline pre-branching. Background technique [0002] Under the current background technical conditions, there are two different processor instruction set architectures, namely RISC and CISC (that is, "reduced instruction set" and "complex instruction"). However, in fact, the real difference is the hardware implementation of the instruction sets of the two camps, that is, the circuit implementation of the pipeline. [0003] The hardware corresponding to RISC implements the basic operations required by programs such as operations, instruction / data reading, and data writing based on more "programming registers". All operations of RISC are completed based on "programming registers", so the goal of RISC is actually to make the circuit structure simpler, so the core pipeline structure adopted by the RISC camp is a simple pipeline structure, that...

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Problems solved by technology

[0008] However, under the existing background technical conditions, whether the pipeline hardware of the two "threads" existing in the kernel is actually used by the "threads" depends on the scheduling of the operating system, that is, the program itself cannot be sure that all pipeline hardware resources are available. Can be used for branch prediction

Therefore, under the current background technical conditions, unless the software, especially the system software, can do more "coordination" or "synchronization", theoretically it can be realized that the program can be sure whether all pipeline hardware resources can be used for branch prediction, But in this way, it does not have the meaning of actually improving efficiency (so, in fact, under the existing background technology conditions, the high-end processing core does not realize more threads than 2 threads, that is, pipeline hardware resources, precisely because of the realization of More "threads" whose functions are too single

Single-threaded multi-branch applications, which account for the majority of applications, will cause excessive cost and waste of power consumption due to excessive pipeline hardware resources being in a useless state)

In addition, even if the existing background technology realizes the above-mentioned theoretical possibility, the existing background technology still cannot solve the problem of ultra-long pipeline branch prediction well, because in practical applications, within the execution time of a single instruction (instruction from entering pipeline to generate output), there will be a high probability that there will be multiple binary tree branch points in the pipeline, so before the result of the conditional jump instruction, after the second binary tree branch point enters the pipeline, it can still only be 50% correct sex probability assumptions

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