Stacked Cache system based on SEDRAM, control method and Cache device

Abstract

The invention relates to a stacked Cache system based on an SEDRAM, a control method and a Cache device, the stacked Cache system is integrated on a multi-layer bonding wafer and comprises a cache memory, a Cache controller and an SEDRAM controller; wherein the multi-layer bonding wafer comprises a storage wafer structure and a processor wafer structure; the SEDRAM unit is integrated in each layerof storage wafer in the storage wafer structure and is used as a storage space of the high-speed buffer memory; the processor wafer structure is integrated with a CPU, a Cache controller, an SEDRAM controller and a memory controller. According to the Cache system, the SEDRAM unit integrated on each layer of storage wafer of the storage wafer structure is used as the storage space of the cache memory, so that the capacity and bandwidth of the cache memory can be greatly improved, the hit rate of the cache memory is increased, the reading speed of hot spot data is increased, the hit rate of data read in a CPU is increased, and meanwhile, storage resources of the processor chip can be saved.

Description

technical field [0001] The invention relates to the technical field of computer memory, in particular to a stacked Cache system based on SEDRAM, a control method and a Cache device. Background technique [0002] In the prior art, cache memory (Cache) is a small-capacity high-speed memory composed of fast SRAM (Static Random-Access Memory) storage elements, which can be directly integrated in a CPU (Central Processing Unit, central processing unit) chip. A high-speed cache is set between the CPU and the memory, and the frequently accessed active program blocks and data blocks in the memory are copied to the cache to improve the speed of CPU read and write instructions and data. Due to the locality of program access, in most cases, the CPU can directly obtain instructions and data from the Cache without accessing the memory. [0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designe...

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Problems solved by technology

[0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designed to be smaller, but SRAM requires a large volume, and the price is relatively high. An important reason for increasing the cache capacity. The increase in capacity will inevitably lead to an increase in the number of transistors inside the CPU. To integrate a larger cache on a limited CPU area, the manufacturing process is more demanding.

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