Autonomous controllable data communication gateway machine based on double high-speed buses and communication method

A technology of a data communication network and a communication method, which is applied to an autonomously controllable data communication gateway based on dual high-speed buses and the field of communication, which can solve problems such as RAM access bottlenecks, achieve the effect of liberating performance bottlenecks and alleviating data processing capabilities

Pending Publication Date: 2021-03-26
国家电网有限公司能源互联网技术研究院 +4
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] The purpose of the present invention is to provide an autonomously controllable data communication gateway machine and a commun

Method used

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  • Autonomous controllable data communication gateway machine based on double high-speed buses and communication method

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Experimental program
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Effect test

Embodiment 1

[0053] see figure 1 As shown, the present invention provides an autonomously controllable data communication gateway based on dual high-speed buses, including: a CPU, a first PCI-E bus, a second PCI-E bus and a third PCI-E bus. The first PCI-E bus is a high-speed bus of PCI-E3.0, the second PCI-E bus is a high-speed bus of PCI-E3.0, and the third PCI-E bus is a low-speed bus of PCI-E1.0.

[0054] The first PCI-E bus adopts FT PCI-E3.0 high-speed bus.

[0055] The first PCI-E bus (FT PCI-E3.0 high-speed bus) is connected to the CPU (FT2000+) through the PCI-E3.0×8 interface, and receives commands and returns data;

[0056] The first PCI-E bus (FT PCI-E3.0 high-speed bus) is connected to the domestic RAM through DDR4, and the cache data is read and written through Bank / Row Active and IO;

[0057] The first PCI-E bus (FT PCI-E3.0 high-speed bus) is connected with the domestic ETH0-5 through the network port LAN0-5 to process network requests and network data;

[0058] The firs...

Embodiment 2

[0070] The present invention also provides a communication method for an autonomously controllable data communication gateway based on dual high-speed buses. Based on the autonomously controllable data communication gateway based on dual high-speed buses described in Embodiment 1, the communication method includes:

[0071] The first PCI-E bus communicates with the random access memory RAM, and handles cache data reading and writing through Bank / Row Active and IO; the first PCI-E bus is dedicated to RAM access, and is used to solve the bottleneck of device access to RAM ;

[0072] The first PCI-E bus communicates with the network port to process network requests and network data;

[0073] The first PCI-E bus communicates with the third PCI-E bus, and receives the request and response of the low-speed response device collected by the third PCI-E bus to the random access memory RAM;

[0074] The first PCI-E bus communicates with the CPU, receives commands and returns data;

[...

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Abstract

The invention provides an autonomous controllable data communication gateway machine based on double high-speed buses and a communication method, and the data communication gateway machine comprises:a first PCI-E bus which is connected with a random access memory RAM and a network interface; a second PCI-E bus which is connected with the logical operation unit; a third PCI-E bus which is connected with all the low-speed response devices; and a CPU which is connected with the first PCI-E bus, the second PCI-E bus and the third PCI-E bus. The double PCI-E high-speed bridges are used for simulating the double north bridges, the single PCI-E low-speed bridge is used for simulating the single south bridge, and the first PCI-E bus is specially used for RAM access, so that the bottleneck of RAMaccess of equipment is solved.

Description

technical field [0001] The invention relates to the technical field of automation control, in particular to an autonomously controllable data communication gateway machine and a communication method based on dual high-speed buses. Background technique [0002] Regardless of the significance of the national economy and the people's livelihood of the chip or the huge economic profit benefits, the construction of the domestic chip industry chain is indispensable; at present, with the rise of some Chinese embedded design manufacturers, they are approaching developed countries in many fields. The level of technology has also surpassed the advanced foreign technology in terms of memory chips. In terms of general-purpose computing chips, the gap between domestic chip design level and quality and developed countries has narrowed year by year, and the cost performance is higher. The current main technical architecture: ARM, X86, MIPS, PowerPC, RISC-5, etc. In the embedded field, AR...

Claims

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Application Information

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IPC IPC(8): G06F13/40G06F13/42G06F9/38G06F15/16
CPCG06F13/4027G06F13/4282G06F9/3836G06F15/16G06F2213/0026
Inventor 徐歆姚志强窦仁晖樊陈任浩倪益民杨青耿明志
Owner 国家电网有限公司能源互联网技术研究院
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