Double-voltage dynamic configuration hardware circuit structure based on multi-bit approximate adder

Abstract

The invention provides a double-voltage dynamic configuration hardware circuit structure based on a multi-bit approximate adder, which belongs to the technical field of calculation, reckoning or counting. The hardware circuit structure comprises an input element acquisition module, an approximate bit width configuration module, a dual-supply voltage dynamic configuration module and an error detection module. Specificall, firstly, tolerable errors and input data bit width of a system needing to be configured are obtained, approximate bit width configuration on a multi-bit approximate adder is conducted, and the approximate bit width is compared with the tolerable errors of the system in the process of dynamically adjusting the approximate bit width, so that the approximate adder configuresthe maximum approximate bit width under the condition of meeting the system error requirement, and the object of reducing power consumption is achieved. And then the power supply voltage of the approximate calculation part is adjusted based on the configured approximate bit width, the power consumption can be effectively reduced by reducing the power supply voltage of the approximate calculation part, and error detection is continuously carried out in the dynamic adjustment process of the power supply voltage, so that the correctness is ensured.

Description

technical field [0001] The invention discloses a dual power supply voltage dynamic configuration hardware circuit structure based on a multi-bit approximate adder, relates to the field of low power consumption approximate calculation, and belongs to the technical field of calculation, calculation or counting. Background technique [0002] With the progress and development of digital integrated circuits, chip power consumption has increased significantly. The requirements of practical application engineering for mobile computing and chip integration density are increasing day by day, and power consumption has become a key design constraint. Traditional circuit design adopts a completely accurate calculation circuit structure, but some application engineering with fault tolerance (such as multimedia processing, pattern recognition and machine learning, etc.) has a certain tolerance for limited or unimportant errors in the calculation process. Fault tolerance arises from a num...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art, and propose a dual-voltage dynamic configuration hardware circuit structure based on a multi-bit approximate adder, and reasonably divide the approximate bit width according to the tolerable error of the configured system. The approximate calculation part of the bit approximate adder is configured with a reasonable low power supply voltage, which can significantly reduce power consumption without affecting the accuracy of calculation, and solve the problem that traditional accurate calculation circuits and approximate addition circuits cannot guarantee accuracy and lower power consumption technical issues

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