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Clock oscillator circuit, charge pump circuit and Flash chip

A technology of clock oscillator and charge pump, which is applied in the direction of electric pulse generator circuit and conversion equipment without intermediate conversion to AC, which can solve the problem of charge pump voltage overshoot and so on.

Inactive Publication Date: 2021-04-09
XTX TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a clock oscillator circuit, a charge pump circuit and a Flash chip, aiming to solve the problem of overshooting of the charge pump voltage caused by one more falling edge or rising edge of the clock pulse when the existing clock oscillator is enabled and closed The problem

Method used

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  • Clock oscillator circuit, charge pump circuit and Flash chip
  • Clock oscillator circuit, charge pump circuit and Flash chip
  • Clock oscillator circuit, charge pump circuit and Flash chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] like image 3 As shown, in some specific embodiments, the level holding module A1 includes a first NAND gate 1, a second NAND gate 2, and a first NAND gate 3, and the first NAND gate 1 of the first NAND gate The input terminal is connected to the first clock pulse CLK output by the clock oscillator OSC, the second input terminal of the first NAND gate 1 is connected to the output terminal of the second NAND gate 2, and the output terminal of the first NAND gate 1 is connected to the first NAND gate. The input terminal of gate 3, the output terminal of the first NOT gate 3 is connected to the input terminal of the charge pump, the output terminal of the first NAND gate 1 is connected to the first input terminal of the second NAND gate 2, and the clock enable EN passes through The logic processing of the seventh NOT gate 4 is input to the second input end of the second NAND gate 2 .

Embodiment 2

[0034] like Figure 4 As shown, in some specific embodiments, the level holding module A1 includes a second NOT gate 5, a third NAND gate 6, a fourth NAND gate 7 and a third NOT gate 8, and the second NOT gate The input terminal of the gate 5 is connected to the first clock pulse CLK output by the clock oscillator OSC, the output terminal of the second NOT gate 5 is connected to the first input terminal of the third NAND gate 6, and the second input terminal of the third NAND gate 6 terminal is connected to the output terminal of the fourth NAND gate 7, and the clock enable EN is input to the second input terminal of the fourth NAND gate 7 after logic processing of the seventh NAND gate 4, and the first input terminal of the fourth NAND gate 7 terminal is connected to the output terminal of the third NAND gate 6, the output terminal of the third NAND gate 6 is connected to the input terminal of the third NOT gate 8, and the output terminal of the third NOT gate 8 is connected ...

Embodiment 3

[0036] Such as Figure 5 As shown, in some specific embodiments, the level holding module A1 includes a first NOR gate 9, a second NOR gate 10 and a fourth NOR gate 11, and the first NOR gate 9 of the first NOR gate The input terminal is connected to the first clock pulse CLK output by the clock oscillator OSC, the second input terminal of the first NOR gate 9 is connected to the output terminal of the second NOR gate 10, and the output terminal of the first NOR gate 9 is connected to the second OR The first input terminal of the NOT gate 10, the clock enable EN is input to the second input terminal of the second NOR gate 10 after the logic processing of the seventh NOT gate 4, and the output terminal of the first NOR gate 9 is connected to the fourth NOT gate. The input terminal of the gate 11 and the output terminal of the fourth NOT gate 11 are connected to the input terminal of the charge pump.

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Abstract

The invention discloses a clock oscillator circuit, a charge pump circuit and a Flash chip, a first clock pulse CLK generated by a clock oscillator OSC is not directly input to a charge pump Charge Pump, but is processed by a level maintaining module to obtain a second clock pulse CLKm, then the second clock pulse CLKm is input to the charge pump Charge Pump, and the original level can be maintained after a clock enabling EN is equal to 0. Therefore, the clock pulse received by the charge pump Charge pump is equal to the previous received clock pulse, and the problem of overshoot of the output voltage VPP of the charge pump Charge pump due to the clock is prevented.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a clock oscillator circuit, a charge pump circuit and a Flash chip. Background technique [0002] In the peripheral circuit of Flash, the charge pump provides Flash with high voltage or negative voltage required for reading, writing, and erasing. The voltage generated by the charge pump, such as the voltage for Flash Word Line, requires adjustable voltage, short settling time, and low ripple. Small, especially in read operations, the requirements for ripple are more stringent. [0003] like figure 1 As shown, usually after the output voltage VPP of the charge pump reaches the target voltage, the enable EN of the clock oscillator OSC will be turned off, that is, the input of the clock CLKx (x=0 or 1) will be turned off, the charge pump will stop working, and the output voltage VPP will not change. will rise again. However, in practical applications, th...

Claims

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Application Information

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IPC IPC(8): H03K3/02H02M3/07
CPCH02M3/07H03K3/02
Inventor 吴彤彤王小光龙冬庆
Owner XTX TECH INC
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