IP core for achieving ASI interface function based on FPGA resources

Abstract

The invention discloses an IP core for achieving an ASI interface function based on FPGA resources, and relates to the technical field of FPGAs, the IP core comprises a sending module and a receiving module, the sending module processes user parallel data into a data format conforming to an ASI standard through a data packaging unit, a coding unit and a serialization processing unit; the receiving module processes data received by the ASI interface into parallel data convenient for a user to use by using an oversampling deserializing unit, a data extraction unit, a word alignment unit, a decoding unit and a synchronization unit; the IP core uses a small amount of FPGA internal resources when realizing the transceiving function, other functions are achieved by soft logic without depending on off-chip hardware resources, the system cost and power consumption can be reduced, and the data is packaged into an IP core form convenient to use, the IP core has portability and reusability, and is convenient to update and upgrade.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to an IP core for realizing ASI interface functions based on FPGA resources. Background technique [0002] At present, asynchronous serial interface (ASI interface) and synchronous parallel interface (SPI interface) are two common MPEG-2 video transmission methods. The SPI interface has a total of 11 useful signals, and each signal is transmitted in a differential form to improve Transmission anti-interference, so the connection is many and complicated, the transmission distance is short, and it is prone to failure. The ASI interface has a constant transmission rate, less connections, and is convenient for long-distance transmission. Therefore, in the DVB system, the ASI interface is widely used in point-to-point transmission because of its high speed, reliability, and accuracy. [0003] At present, a dedicated ASI chip is usually used to implement the ASI interface. For example, the...

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Problems solved by technology

[0003] At present, a dedicated ASI chip is usually used to implement the ASI interface. For example, the ASI sender chip CY7B923 and the ASI receiver chip CY7B933 of CYPRESS are usually used at present, but the use of a dedicated ASI chip will increase the power consumption and cost of the overall system

Another way is to use programmable logic devices such as CPLD or FPGA to realize the ASI interface, but in the prior art, the ASI interface is implemented based on the ASI core of the IP library of the programmable logic device, which makes it only possible to provide corresponding functions Only programmable logic devices with IP cores (such as ALTERA's FPGA) can realize the above-mentioned ASI interface, while programmable logic devices that do not provide corresponding functional IP cores (such as Xilinx's FPGA) cannot realize the ASI interface, which is limited by the device itself More robust, less portable

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