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Multi-layer stacked packaging structure and preparation method of multi-layer stacked packaging structure

A packaging structure and multi-layer stacking technology, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc. Limitation and other issues, to achieve the effect of heat dissipation and wire bonding, increase the number of stacks, and reduce the size of the package

Active Publication Date: 2021-05-07
FOREHOPE ELECTRONICS NINGBO CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This kind of stacked product (memory card / memory card) usually has two types of chips, a memory chip and a control chip, which are packaged in the same substrate unit by stacking, which cannot effectively use the two-dimensional / three-dimensional rotating space for stacking , For example: NAND products require a large enough product capacity and a large number of stacked layers, and the performance of its memory card is limited by the number of memory chips and the size of the stacked structure

Method used

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  • Multi-layer stacked packaging structure and preparation method of multi-layer stacked packaging structure
  • Multi-layer stacked packaging structure and preparation method of multi-layer stacked packaging structure
  • Multi-layer stacked packaging structure and preparation method of multi-layer stacked packaging structure

Examples

Experimental program
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Effect test

no. 1 example

[0048] see in conjunction Figure 1 to Figure 7 , this embodiment provides a multi-layer stacked packaging structure 100, which adopts a bidirectional spiral stacking method, which can increase the number of stacks, reduce the size of the stack, ensure the stability of the structure, and increase the integration of the product.

[0049] The multilayer stack package structure 100 provided in this embodiment includes a substrate 110, a first base chip 130, a second base chip 150, a plurality of first structure chips 171, a plurality of second structure chips 181 and a plastic package 190, the first The base chip 130 and the second base chip 150 are mounted on the substrate 110, and the first base chip 130 and the second base chip 150 are centrally symmetrically arranged, and the first base chip 130 and the second base chip 150 are electrically connected to the substrate 110 . A plurality of first structure chips 171 are mounted on the first base chip 130, and the plurality of f...

no. 2 example

[0068] see Figure 8 , a multi-layer stack package structure 100 provided in this embodiment, its basic structure, principle and technical effects are the same as those of the first embodiment. Corresponding content in the embodiment.

[0069] In this embodiment, the multilayer stack package structure 100 includes a substrate 110, a first base chip 130, a second base chip 150, a plurality of first structure chips 171, a plurality of second structure chips 181 and a plastic package 190, the first The base chip 130 and the second base chip 150 are mounted on the substrate 110, and the first base chip 130 and the second base chip 150 are centrally symmetrically arranged, and the first base chip 130 and the second base chip 150 are electrically connected to the substrate 110 . A plurality of first structure chips 171 are mounted on the first base chip 130, and the plurality of first structure chips 171 are spirally stacked on the first base chip 130, and form an electrical conne...

no. 3 example

[0076] This embodiment provides a multi-layer stack package structure 100. Its basic structure, principle and technical effect are the same as those of the first embodiment. For a brief description, the part not mentioned in this embodiment can refer to the first embodiment corresponding content in the example.

[0077] The multilayer stack package structure 100 provided in this embodiment includes a substrate 110, a first base chip 130, a second base chip 150, a plurality of first structure chips 171, a plurality of second structure chips 181, and a plastic package 190. The first base The chip 130 and the second base chip 150 are mounted on the substrate 110 , and the first base chip 130 and the second base chip 150 are arranged symmetrically to the center, and the first base chip 130 and the second base chip 150 are electrically connected to the substrate 110 . A plurality of first structure chips 171 are mounted on the first base chip 130, and the plurality of first structu...

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PUM

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Abstract

An embodiment of the invention provides a multi-layer stacked packaging structure and a preparation method of the multi-layer stacked packaging structure, and relates to the field of chip packaging. The multi-layer stacked packaging structure comprises a substrate, a first substrate chip, a second substrate chip, a plurality of first structure chips, a plurality of second structure chips and a plastic package body, wherein the first substrate chip and the second substrate chip are symmetrically mounted, meanwhile, the plurality of first structure chips are spirally stacked to form a first spiral structure, and the plurality of second structure chips are spirally stacked to form a second spiral structure, so that the plurality of first structure chips and the plurality of second structure chips rotate and are upwards stacked in a staggered manner. By adopting the central symmetry and spiral stacking mode, the plurality of second structure chips can be stacked on the first substrate chip at the same time, the stacking number is increased, the packaging size is reduced, heat dissipation and routing of the structure are facilitated through the spiral staggered stacking mode, meanwhile, the stability of the structure is guaranteed, and the integration degree of the product is increased.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a multilayer stack packaging structure and a preparation method of the multilayer stack packaging structure. Background technique [0002] With the rapid development of the semiconductor industry, the miniaturization of electronic products is becoming thinner and thinner to meet the needs of users and the product performance and memory are getting higher and higher. Therefore, the semiconductor packaging structure adopts multiple chip stacking (Stack-Die) technology or chip The FOW (flow over wire) technology stacks two or more chips in a single package structure to reduce the size of the product package and improve product performance. This kind of stacked product (memory card / memory card) usually has two types of chips, a memory chip and a control chip, which are packaged in the same substrate unit by stacking, which cannot effectively use the two-dimensional / three-dimen...

Claims

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Application Information

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IPC IPC(8): H01L25/18H01L23/31H01L21/50H01L21/56
CPCH01L21/50H01L21/56H01L23/3114H01L25/18
Inventor 吴春悦何正鸿
Owner FOREHOPE ELECTRONICS NINGBO CO LTD
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