NMOS transistor, manufacturing method thereof and three-dimensional heterogeneous integrated chip

Abstract

The invention discloses an NMOS transistor, a manufacturing method thereof and a three-dimensional heterogeneous integrated chip, relates to the technical field of semiconductors, and aims at reducing the activation temperature of N-type impurities when a germanium-based NMOS transistor is manufactured, preventing performance degradation of a bottom layer device included in the three-dimensional heterogeneous integrated chip when the germanium-based NMOS transistor is used as an upper-layer device included in the three-dimensional heterogeneous integrated chip, and improving the working performance of the three-dimensional heterogeneous integrated chip. The manufacturing method of the NMOS transistor comprises the step of forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is made of germanium; doping N-type impurities into the source region forming region and the drain region forming region of the fin-shaped structure; forming a metal layer at least covering the source region forming region and the drain region forming region; and performing low-temperature annealing on the substrate on which the fin-shaped structure and the metal layer are formed so as to respectively form a source region and a drain region in the source region forming region and the drain region forming region, forming a first metal contact layer on the source region, and forming a second metal contact layer on the drain region.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an NMOS transistor, a manufacturing method thereof, and a three-dimensional heterogeneous integrated chip. Background technique [0002] In the field of semiconductors, germanium materials have high and symmetrical carrier rates. Meanwhile, the forbidden band width of germanium is smaller than that of silicon. Based on this, when a germanium-based substrate is used to manufacture a transistor, the transistor can have a larger driving current, a faster switching speed and a lower driving voltage. Moreover, germanium material has natural low-temperature process advantages, making germanium-based transistors the first choice for manufacturing upper-layer devices included in three-dimensional heterogeneous integrated chips. [0003] However, in the case of adopting the existing manufacturing method and using germanium-based NMOS transistors as the upper device included in th...

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Problems solved by technology

[0003] However, in the case of using the existing manufacturing method and using germanium-based NMOS transistors as the upper device included in the three-dimensional heterogeneous integrated chip, it will cause performance degradation of the bottom device included in the three-dimensional heterogeneous integrated chip

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