Forming method of transistor device layout

Abstract

The invention provides a forming method of a transistor device layout. The forming method is characterized in that the distance between a first floating gate pattern and an active region pattern is increased by shortening the length of the first floating gate pattern in a first direction, so that in a manufacturing process of a transistor device, the distance between a floating gate formed by adopting the floating gate pattern and an active region formed by adopting the active region pattern can be increased, so that a shadow region can be avoided, electric leakage can be reduced, and the power consumption of a transistor device can be reduced; and design rule check is carried out on the reduced first floating gate pattern to determine whether the length of the reduced first floating gate pattern in the first direction accords with a design rule, if not, extension processing is carried out on the first floating gate pattern in the first direction along a direction far away from the active region pattern, so that the length of the first floating gate pattern in the first direction is increased, and the situation that the size of the floating gate in the manufacturing process corresponding to the floating gate pattern is too small can be avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor device layout. Background technique [0002] refer to figure 1 , which is a structural schematic diagram of a transistor device in the prior art. Such as figure 1 As shown, the existing transistor device includes: a substrate 10, an active region 11 located in the substrate 10, and a floating gate 12 located on the active region 11, and the floating gate 12 includes a first part 13 and the second portion 14, the first portion 13 of the floating gate 12 is perpendicular to the second portion 14, and the first portion 13 of the floating gate 12 is parallel to the active region 11, the second portion of the floating gate 12 14 covers a part of the active region 11, but there is a shadow region 15 in the active region 11, and the shadow region 15 will cause electric leakage and make the power consumption of the transistor devic...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a method for forming the layout of a transistor device, so as to solve the problems of shadow areas and large power consumption in the existing transistor devices

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