Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effects of avoiding adverse effects, improving production yield, and improving warpage changes

Active Publication Date: 2021-06-25

CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO LTD

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AI-Extracted Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and...

Method used

Provide another wafer with larger warpage in the stretching direction during the intermediate process, the stretching direction of the warpage of the wafer reaches 0.334mm deformation, and the back film of the wafer is doped polysilicon plus gate oxide layer. Usually, those skilled in the art improve the warpage by adding a film layer. The inventors of this case tried to remove the doped polysilicon on the back of the wafer to study the change of the warpage of the wafer. Since there is another silicon dioxide film layer between the polysilicon on the back and the back of the wafer, this silicon dioxide film will also be removed if wet etching is used, so dry etching is used to remove the gate oxide layer on the back of the wafer. After etching, the polysilicon is etched away. Comparing the front and rear curvature radii of the wafer, the inventors of this case unexpectedly found that reducing the doped polysilicon layer on the back of the wafer can also achieve the effect of improving the warpage of the wafer. The improvement reached 15%. Compared with the traditional solution of increasing the film layer to improve the warpage of the wafer, reducing the doped polysilicon layer on the back of the wafer can not only reduce the warpage deformation in the stretching ...

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps that: a wafer is provided, the wafer comprises a front surface used for forming a semiconductor device and a back surface opposite to the front surface, a doped polycrystalline silicon layer is grown on the back surface of the wafer, and the wafer has a first warping degree; and the doped polycrystalline silicon layer is removed, so that the wafer has a second warping degree, and the second warping degree is smaller than the first warping degree. According to the semiconductor structure and manufacturing method thereof of the invention, the polycrystalline silicon film layer on the back surface of the wafer is reduced, so that the warping degree change in the stretching direction of the wafer can be improved; in addition, after the polycrystalline silicon film layer on the back face of the wafer is removed, the silicon dioxide layer is further formed on the back face of the wafer; under the condition that the total thickness of the wafer is not increased or even reduced, the warping degree change of the wafer in the stretching direction can be further improved, and adverse effects caused by increase of the thickness of the wafer are avoided. The wafer warping degree is improved, so that the subsequent process can be carried out smoothly, and the production yield can be improved.

Application Domain

Semiconductor/solid-state device manufacturing

Technology Topic

PhysicsPolycrystalline silicon +7

Image

Examples

Experimental program(4)

Example Embodiment

[0062] Example one

[0063] In this embodiment, a method of making a semiconductor structure, see figure 1 The process flow diagram showing the method, including the following steps:

[0064] A wafer is provided which includes a front surface for forming a semiconductor device and a back surface of the front surface having a first tapered curvature, and the wafer is grown with a doped polysilicon layer;

[0065] The doped polysilicon layer was removed such that the wafer had a second tippening, and the second warpage curvature was smaller than the first tape.

[0066] First see figure 2 , Performing step S1: Provides a wafer 1 having a first tapered curvature, and the wafer 1 is provided with a doped polysilicon layer 3.

[0067] As an example, in the direction of the back surface of the wafer 1, the wafer 1 is sequentially provided with a first silicon dioxide layer 2, the doped polysilicon layer 3, and a second bis silicon oxide layer 4, which The thickness of the doped polysilicon layer 3 is greater than the thickness of the second silicon oxide layer 4.

[0068] It should be noted that the membrane layer on the back surface of the wafer 1 is non-deliberately formed, but the passive formation (e.g., a furnace deposition method) during the front surface of the wafer forming the corresponding film layer. In this embodiment, the wafer 1 is also provided with a front polysilicon layer (not shown) formed in synchronized with the doped polysilicon layer 3 and a gate oxide layer formed synchronously with the second bis silicon oxide layer 4. (Not shown).

[0069] Then please refer to image 3 and Figure 4 , Perform step S2: Removing the doped polysilicon layer 2 so that the wafer 1 has a second warpage curvature, the second tipping curvature is less than the first tape.

[0070] It should be noted that the first silica layer 2 is also provided in the back surface of the wafer 1 and the doped polysilicon layer 3, and the silica film layer is also used by wet etching. And removing, this step is preferably used to remove the doped polysilicon layer 2 by dry etching.

[0071] In this embodiment, the second silicon oxide layer 4 (eg, image 3 The desired polycrystalline silicon layer 3 (eg, as shown) and continues to remove the doped polysilicon layer 3 (eg Figure 4 Indicated).

[0072] It should be pointed out that although the stress of silica is opposite to the stress of the doped polysilicon itself, since the thickness of the doped polysilicon layer 3 is larger than the thickness of the second silicon oxide layer 4, the doped polysilicon is removed. The degree of warpage at layer 3 is greater than the degree of warpage of the second bis silicon oxide layer 4, and the overall warpage of the wafer 1 is still reduced.

[0073] The method of fabricating the semiconductor structure of the present embodiment can improve the warpage change in the wafer stretch direction by reducing a layer of doped polysilicon layer on the back side of the wafer, and does not increase the thickness of the wafer thickness, can avoid the increase in wafer thickness The adverse effect. The improvement in wavy curvature makes the subsequent process can be carried out smoothly, which is advantageous to enhance the production yield.

Example Embodiment

[0074] Example 2

[0075] The present embodiment is a substantially the same technical solution as the embodiment, and the present embodiment further forms a silica layer after removing the doped polysilicon layer, further forming a silica layer on the back surface of the wafer, so that the wafer Has a third hempet, the third hemodiacity is smaller than the second warpage.

[0076] First see Figures 2 to 4 , Perform the substantially the same steps S1-S2 as the embodiment.

[0077] See Figure 5 and Figure 6 Further, the silica layer is further formed on the back surface of the wafer 1.

[0078] Specifically, since the chemical gas phase cannot form a silicon dioxide layer on the back surface of the wafer, the positive surface of the wafer 1 and the back surface are respectively formed in the front and back surfaces of the wafer 1 and the back surface, respectively. Layer 6 (eg Figure 5 The front silica layer 5 is removed by dry etching.

[0079] As an example, after the silica layer is formed, the total thickness of the wafer is less than or equal to the total thickness of the wafer prior to removal of the doped polysilicon layer.

[0080] As an example, the thickness range of the silica layer is 200 nm to 1500 nm.

[0081] This embodiment can further improve the warpage change in the wafer stretch direction, and the total thickness of the wafer does not increase, even decreased, and can avoid the adverse effect of the wafer thickness. Improvement of wavy curvature makes the subsequent process can be carried out more smoothly, further increasing the production level.

Example Embodiment

[0082] Example three

[0083] In this embodiment, a semiconductor structure is provided, and the semiconductor structure uses a method of fabricating the semiconductor structure as described in the embodiment in its manufacturing process.

PUM

Property	Measurement	Unit
Thickness	200.0 ~ 1500.0	nm

Description & Claims & Application Information

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Classification and recommendation of technical efficacy words

avoid adverse effects

Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., to achieve the effects of avoiding adverse effects, improving production yield, and improving warpage changes

AI-Extracted Technical Summary

Problems solved by technology

Method used

Abstract

Image

Examples

Example Embodiment

Example Embodiment

Example Embodiment

PUM

Description & Claims & Application Information

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