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Micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and preparation method thereof

A wafer-level packaging, vertical interconnection technology, applied in microstructure technology, microstructure devices, manufacturing microstructure devices, etc., can solve problems such as large wafer area or size

Active Publication Date: 2021-07-06
SOUTH CHINA AGRI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing MEMS three-dimensional wafer-level packaging form with a low-resistance silicon body as a vertical interconnection path faces the following problems: the vertical interconnection structure of a low-resistance silicon body either requires insulating trenches to be densely filled with insulating substances to ensure that the MEMS The airtightness of the package, or a separate sealing ring design for the vertical interconnect structure of the low-resistance silicon body is required to ensure the airtightness of the MEMS package
For example, the invention application with the application publication number of CN 106711121 A discloses a silicon pillar through-hole interconnection structure and its manufacturing method. The cover insulation trench of the silicon pillar interconnection structure requires etching through the cover plate, usually A separate design of a bonding seal ring with a width of several hundred microns is required to realize the isolation of the silicon pillar interconnection structure from the inside of the package, which leads to a larger wafer area or size occupied by the vertical interconnection structure, thereby limiting low-cost Interconnection Density Enhancement and Package Miniaturization of Barrier Silicon Body Vertical Interconnection Structure

Method used

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  • Micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and preparation method thereof
  • Micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and preparation method thereof
  • Micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and preparation method thereof

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Embodiment 1

[0041] The invention relates to a micro-mechanical wafer-level packaging structure with silicon pillars vertically interconnected and a preparation method thereof, which are used to achieve wafer-level vacuum or hermetic packaging of micro-electro-mechanical systems and at the same time realize internal devices and external circuits or circuits in the package. Silicon pillar vertical interconnects and signal interfaces for the device. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

[0042] see figure 1 , is a schematic diagram of ...

Embodiment 2

[0057] see Figure 8 In this embodiment, the device side bonding metal layer 105 and the cover plate side bonding metal layer 201 are not provided with an insulating isolation space 206. This situation is applicable to devices that only need a vertical interconnection of silicon pillars on a cover plate silicon wafer. In the case of the signal interface, that is, only one electrode of the device needs to be drawn out of the package structure.

Embodiment 3

[0059] see Figure 9 In this embodiment, there are two kinds of vertical interconnection structures 208 of silicon pillars. The difference from Embodiment 1 is that another vertical interconnection structure 208 of silicon pillars is used to lead out the electrical signals on the bonding metal layer 105 on the device side. , this situation is applicable to the situation where the device requires a signal interface for vertical interconnection of multiple silicon pillars on the cover plate, that is, the device requires multiple electrodes to be drawn out from the packaging structure, so each electrode needs to be provided with a sealed partition space 206 to realize mutual electrically isolated or independent.

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Abstract

The invention discloses a micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and a preparation method thereof. The packaging structure comprises a micromechanical device structure unit and a cover plate structure unit; a device side bonding metal layer and a cover plate side bonding metal layer are connected with each other to form a bonding structur; a cover plate insulating layer is provided with a cover plate insulating layer window; the cover plate side bonding metal layer is electrically connected with the cover plate silicon wafer through the cover plate insulating layer window; the cover plate silicon wafer and the cover plate top metal are provided with an insulating groove surrounding the periphery of the cover plate insulating layer window, and a bonding structure formed by the device side bonding metal layer and the cover plate side bonding metal layer supports the cover plate insulating layer below the insulating groove; and the cover plate silicon wafer forms a silicon column vertical interconnection structure on the inner side of the insulating groove. An independent bonding sealing ring needed by each silicon column interconnection structure is avoided, the overall wafer occupied area of the silicon column interconnection structure is reduced, the silicon column interconnection density is improved, and miniaturization of the packaging structure is facilitated.

Description

technical field [0001] The invention relates to the fields of micro-electromechanical systems and packaging, in particular to a micro-mechanical wafer-level packaging structure and a preparation method for vertical interconnection of silicon pillars. Background technique [0002] Micro Electro Mechanical System (MEMS) is a general term for micromechanical components formed on silicon or other dielectric wafers through semiconductor technology and micro-nano processing technology, and finally integrated with signal processing circuits. Since the movable structure of MEMS devices is vulnerable to external shocks and environmental impacts in the assembly process and actual application scenarios, it is usually necessary to perform airtight or vacuum packaging to protect the fragile movable structure of the device, achieve isolation from the external environment, and improve device performance. promote. MEMS packaging usually has two packaging solutions: device or chip level (Di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81B7/00B81B7/02B81C1/00
CPCB81B7/0032B81B7/007B81B7/0035B81B7/02B81C1/00261B81C1/00269B81C1/00277B81C1/00301
Inventor 梁亨茂
Owner SOUTH CHINA AGRI UNIV