Micro-mechanical wafer-level packaging structure with vertically interconnected silicon columns and preparation method thereof
A wafer-level packaging, vertical interconnection technology, applied in microstructure technology, microstructure devices, manufacturing microstructure devices, etc., can solve problems such as large wafer area or size
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Embodiment 1
[0041] The invention relates to a micro-mechanical wafer-level packaging structure with silicon pillars vertically interconnected and a preparation method thereof, which are used to achieve wafer-level vacuum or hermetic packaging of micro-electro-mechanical systems and at the same time realize internal devices and external circuits or circuits in the package. Silicon pillar vertical interconnects and signal interfaces for the device. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.
[0042] see figure 1 , is a schematic diagram of ...
Embodiment 2
[0057] see Figure 8 In this embodiment, the device side bonding metal layer 105 and the cover plate side bonding metal layer 201 are not provided with an insulating isolation space 206. This situation is applicable to devices that only need a vertical interconnection of silicon pillars on a cover plate silicon wafer. In the case of the signal interface, that is, only one electrode of the device needs to be drawn out of the package structure.
Embodiment 3
[0059] see Figure 9 In this embodiment, there are two kinds of vertical interconnection structures 208 of silicon pillars. The difference from Embodiment 1 is that another vertical interconnection structure 208 of silicon pillars is used to lead out the electrical signals on the bonding metal layer 105 on the device side. , this situation is applicable to the situation where the device requires a signal interface for vertical interconnection of multiple silicon pillars on the cover plate, that is, the device requires multiple electrodes to be drawn out from the packaging structure, so each electrode needs to be provided with a sealed partition space 206 to realize mutual electrically isolated or independent.
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