Ultralow Phase Noise Clock Buffer

Abstract

The invention relates to the technical field of integrated circuits, in particular to an ultra-low phase noise clock buffer. The ultra-low phase noise clock buffer of the present invention includes a coupling capacitor, a first inverter, a first signal selector, a shaping drive circuit and a signal channel group; the coupling capacitor is used for coupling input signals; the first inverter Including PMOS transistors and NMOS transistors, the channel length of the PMOS transistors and NMOS transistors constituting the first inverter is not less than 5 times the characteristic size; the shaping drive circuit is used to shape the input signal and enhance the driving capability; the signal channel A group includes several groups of signal channels, and the signal channels are used to generate buffered and amplified output clock signals. The present invention can reduce the phase noise to below -100dBc / Hz, even below -120dBc / Hz by designing the overall structure and the unit structure of the buffer.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an ultra-low phase noise clock buffer. Background technique [0002] In devices with wifi and positioning functions, a high-precision synchronous clock is required. The high-precision crystal oscillator itself has no driving capability, and the clock signal needs to be buffered by a clock buffer to increase the driving capability. During the buffering process of the clock signal, phase noise will be generated, so that the accuracy of the clock provided by the device will be deviated. The current technology is generally formed by a phase-locked loop, but the phase noise achieved by this scheme is about -60dBc / Hz, and the phase noise drop is still relatively high. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide an ultra-low phase noise clock buffer, which can reduce the phase noise below -100dBc / Hz, even b...

AI Technical Summary

Problems solved by technology

During the buffering process of the clock signal, phase noise will be generated, so that the clock accuracy provided by the device will deviate.

The current technology is generally composed of a phase-locked loop, but the phase noise achieved by this scheme is around -60dBc / Hz, and the phase noise drop is still relatively high

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