Ultra-low power reset circuit
A reset circuit and ultra-low power consumption technology, applied in the field of ultra-low power reset circuit, can solve the problems of uncontrollable reset point, large static power consumption, large capacitor area, etc., and achieve simple structure, low static power consumption, TRUMPF effect
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[0033] Such as image 3 As shown, the ultra-low power reset circuit of the present invention includes a micro-current bias circuit 1, an inverter INV1, a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2; The current bias circuit 1 is used to generate a bias voltage, and the generated bias voltage provides bias signals to the first NMOS transistor N1 and the second NMOS transistor N2; the bias signal output terminals of the micro current bias circuit 1 are respectively connected to the second The gate of a PMOS transistor P1, the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2, the sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply, and the gates of the first PMOS transistor P1 The drain and the drain of the first NMOS transistor N1 are connected to the gate of the second PMOS transistor P2, and the drain of the second PMO...
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