Secondary high-order advanced successive approximation analog-to-digital converter and control method

Abstract

The invention discloses a secondary high-order advanced successive approximation analog-to-digital converter and a control method. In the successive approximation analog-to-digital converter, a fully differential capacitance type digital-to-analog converter generates reference voltage on an upper pole plate through switching, and when an ADC enters a sampling mode, a secondary high-order lead circuit samples input signals at the same time; after the sampling switch enters a holding state, the ADC performs first comparison to generate the highest bit, and meanwhile, the second high bit advance circuit generates second high bits through comparison, passes through the SAR logic circuit, generates the first two bits at the same time, and then continuously generates subsequent output of the successive approximation analog-to-digital converter from high to low in a successive approximation manner until the whole quantization is finished. According to the invention, through the secondary high-order lead circuit, the conversion period of the ADC is reduced, the number of multiple comparators is reduced, the parasitic capacitance introduced by the input ends of the multiple comparators at the output end of the fully differential capacitive digital-to-analog converter is reduced, the sampling time is reduced, and the conversion rate of the ADC is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a second high bit lead successive approximation analog-to-digital converter and a control method. Background technique [0002] The classic high-speed SAR ADC structure such as figure 1 As shown, it usually works in an asynchronous clock mode. A clock signal is generated inside the ADC to control multiple comparators to work sequentially. This eliminates the comparator reset time of traditional SAR ADCs and reduces the need for high-speed clocks. However, the asynchronous clock that controls the work of the second high-order comparator needs to wait for the high-order conversion to be generated, which increases the conversion delay. The design of multiple comparators also introduces parasitic capacitance at the output of the capacitive DAC, making the sampling Time increases. For example, a SAR ADC with 500Msps and a precision of 6 bits requires 2ns for a single con...

AI Technical Summary

Problems solved by technology

However, the asynchronous clock that controls the work of the second high-order comparator needs to wait for the high-order conversion to be generated, which increases the conversion delay. The design of multiple comparators also introduces parasitic capacitance at the output of the capacitive DAC, making the sampling time increase

For example, a SAR ADC with 500Msps and a precision of 6 bits needs 2ns for a single conversion, 500ps for sampling, and 250ps for a single conversion.

Images