Dynamic compensation method and system for DDR physical layer digital delay chain

Abstract

The invention discloses a dynamic compensation method and system for a DDR physical layer digital delay chain. The dynamic compensation method for the DDR physical layer digital delay chain comprises the following steps: initializing a DDR; acquiring a first latest delay control value of the reference delay chain; if the difference value between the first latest delay control value and the first set delay control value is greater than a preset update threshold value, calculating a working target delay control value of the working delay chain, and generating a working delay chain update signal; in response to the working delay chain update signal and the DDR physical layer being in a temporary idle state, updating the first set delay control value and the second set delay control value according to the working target delay control value. According to the embodiment of the invention, the dynamic adjustment of the working delay chain and the reference delay chain is realized, errors caused by factors such as process, temperature and voltage can be effectively eliminated, the updating signal of the working delay chain is directly responded in the updating process, handshake confirmation with the DDR controller is not needed, and the flow is simpler.

Description

technical field [0001] The invention belongs to the technical field of electronic information, in particular to a DDR physical layer digital delay chain dynamic compensation method and system. Background technique [0002] In the high-speed DDR (Double Rate Synchronous Dynamic Random Access Memory) interface circuit, in order to ensure better data sampling, the JEDEC (Solid State Technology Association is the leading standard organization for the microelectronics industry) The rising or falling edge is placed in the middle of the DQ (data signal). Similarly, when receiving data, it is also necessary to place the rising or falling edge of DQS in the middle of DQ to ensure better reception of samples. A common technique now is to achieve a quarter clock cycle delay by calibrating the delay chain. Therefore, in order to make the delay chain have a relatively fixed and accurate delay, in the DDR initialization stage, the control logic will be set to adjust the number of basic ...

AI Technical Summary

Problems solved by technology

For this reason, the present invention proposes a kind of DDR physical layer digital delay chain dynamic compensation method, and described DDR physical layer digital delay chain dynamic compensation method solves the problem that delay control occurs error due to changes in process, voltage and temperature

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