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Clock and data recovery circuit and signal processing method thereof

A clock signal and circuit technology, applied in the field of clock and data recovery circuit and its signal processing, can solve the problems of digital controller limitation, CDR circuit long loop delay, CDR circuit is not suitable for high-speed application, etc., to achieve delay time reduction, The effect of improving performance

Pending Publication Date: 2021-07-20
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The speed of digital controllers is often limited by conventional semiconductor processes, causing digital-based CDR circuits to suffer from long loop delays
Therefore, conventional digital-based CDR circuits are not suitable for high-speed applications

Method used

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  • Clock and data recovery circuit and signal processing method thereof
  • Clock and data recovery circuit and signal processing method thereof
  • Clock and data recovery circuit and signal processing method thereof

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Embodiment Construction

[0013] Certain terms are used in the description and claims to refer to particular components. Those of ordinary skill in the art should understand that manufacturers of electronic equipment may use different terms to refer to the same component. The specification and claims do not use the difference in name as the way to distinguish components, but use the difference in function of the components as the basis for the difference. "Include" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described herein that a first device is electrically connected to a second device, it means that the first device may be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0014] figure 1 is a schematic diagram...

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Abstract

The invention provides a clock and data recovery (CDR) circuit and a signal processing method thereof. The CDR circuit includes a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Description

technical field [0001] The present invention relates to a clock and data recovery (CDR) circuit, and more particularly, to a clock and data recovery circuit suitable for high-speed applications and a signal processing method thereof. Background technique [0002] In conventional digital-based clock and data recovery (CDR) circuits, loop latency is controlled by a digital controller within the digital-based CDR. The speed of digital controllers is often limited by conventional semiconductor processes, causing digital-based CDR circuits to suffer from long loop delays. Therefore, conventional digital-based CDR circuits are not suitable for high-speed applications. Contents of the invention [0003] Therefore, it is an object of the present invention to provide a digital based CDR circuit which can reduce the overall loop delay time to solve the above-mentioned problems. [0004] According to one embodiment of the present invention, a clock and data recovery (CDR) circuit i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/087H03L7/08H03L7/099
CPCH03L7/087H03L7/0807H03L7/0805H03L7/099
Inventor 高健凯叶泽贤洪仕哲
Owner MEDIATEK INC