Capacitive coupling in a direct-bonded interface for microelectronic devices

Abstract

Capacitive couplings in a direct- bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct- bonded together at the same bonding interface.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of priority to U.S. Patent Application Serial No. 16 / 212,248, filed December 6, 2018, which is an extension of Application Serial No. 16 / 020,654, filed June 27, 2018 Continuation-in-Part of Application No. 16 / 020,654 of U.S. Patent Application No. 15 filed August 25, 2016 claiming the benefit of priority to U.S. Provisional Patent Application No. 62 / 234,022, filed September 28, 2015 / 247,705 (now U.S. Patent No. 10,032,751, published July 24, 2018), all of which are hereby incorporated by reference in their entirety. Background technique [0003] Direct and direct hybrid joints sometimes require critical tolerances. These processes can become more forgiving when various ways of coupling power, ground, and signal lines at the bonding interface can be designed, for example, allowing for some misalignment and allowing for lower critical tolerances in order to Bonding yield provides a m...

AI Technical Summary

Problems solved by technology

[0004] In addition, the size reduction of wafer-level packages and microelectronics is sometimes inhibited by the necessary inclusion of difficult-to-miniaturize components

For example, sometimes packages rely on the relatively large size of discrete capacitors

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