Gate driver with CMOS structure

Abstract

The invention discloses a grid driver with a CMOS structure, which belongs to the field of integrated circuits and comprises an output driving stage, a dead time control circuit, an NMOS control circuit and a PMOS control circuit. The output driving stage comprises a PMOS transistor P1 and an NMOS transistor N1, and a drain electrode of the PMOS transistor P1 is connected with a drain electrode of the NMOS transistor N1 to serve as an output end OUT of the CMOS driver; the dead time control circuit comprises a first logic unit, a second logic unit, a third logic unit and a fourth logic unit; the second logic unit is connected with the grid electrode of the PMOS transistor P1, and the fourth logic unit is connected with the grid electrode of the NMOS transistor N1; the NMOS control circuit is connected with the third logic unit; and the PMOS control circuit is connected with the first logic unit. The grid electrodes of the PMOS transistors and the grid electrodes of the NMOS transistors in the first logic unit and the third logic unit are separated, and the NMOS transistors in the second logic unit and the PMOS transistors in the fourth logic unit form a cross coupling structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a gate driver with a CMOS structure. Background technique [0002] Complementary metal-oxide-semiconductor field-effect transistor (CMOS) drivers are currently used in a wide variety of electronic applications. A CMOS driver typically consists of a p-channel metal-oxide-semiconductor field-effect transistor (PMOS transistor) and an n-channel oxide-semiconductor field-effect transistor (NMOS transistor) connected in series. The source terminal of the PMOS transistor is connected to the power supply, the source terminal of the NMOS transistor is connected to the ground, the drains of the two transistors are connected to each other, and are used as output terminals, and the gates of the two transistors can also be connected to each other, driven by the front stage rail-to-rail. [0003] The design of CMOS drivers faces various challenges. For example, a CMOS driver may...

AI Technical Summary

Problems solved by technology

Due to this structure and its limited dead time, there is a possibility that the PMOS transistor 108 and the NMOS transistor 110 are turned on at the same time, causing a shoot-through current

[0008] In addition, the gate of the PMOS transistor P12 and the gate of the NMOS transistor N12 in the first logic unit I1 are interconnected, driven by a rail-to-rail signal, and a current path from the power supply VDD to GND via P11, P12, and N12 is very likely to occur.

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