Semiconductor memory device having plurality of banks
A storage body and memory technology, which is applied in the direction of semiconductor devices, static memory, digital memory information, etc., and can solve the problem of increasing the circuit area of the timing control circuit
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no. 1 example
[0144] FIG. 7 is a block diagram showing the structure of the semiconductor memory according to the first embodiment of the present invention. The same numbers as in Fig. 4 denote the same parts.
[0145] The semiconductor memory of the first embodiment consists of memory banks 1 to 4, and latch circuits 6 arranged opposite to memory banks 1 to 4 respectively. 1 to 6 4 , a row address buffer 45, a bank decoder 43, and a timing control circuit 35.
[0146] The timing control circuit 35 is composed of an activation timing chain 37 and a pre-charging timing chain 36 . When a row address activation signal 30 becomes active, timing is predetermined in a predetermined order, an activation timing chain 37 controls a word line drive signal setting signal 10, a precharge signal reset signal 14, and a sense amplifier enabling signal setting signal 15 .
[0147] When a row address inactive signal 31 becomes active, in predetermined order and timing, the precharge timing chain 36 cont...
no. 2 example
[0184]A semiconductor memory according to a second embodiment of the present invention will be described below.
[0185] FIG. 12 is a block diagram showing the structure of a semiconductor memory according to a second embodiment of the present invention. The same reference numerals as in Fig. 7 denote the same components.
[0186] The semiconductor memory of the second embodiment differs from the semiconductor memory of the first embodiment shown in FIG. 7 in that the latch circuit 66 1 to 66 4 Instead of latch circuit 6 1 to 6 4 , banks 61 to 64 instead of banks 1 to 4, and a precharge bank decoder 44 are newly added. That is, the active bank and the precharged bank work independently.
[0187] The precharge bank decoder 44 changes the precharge bank selection signal 47 corresponding to the bank specified by the precharge bank address contained in the address signal 32 and designating the bank to be precharged. 1 to 47 4 to H.
[0188] Compare latch circuit 6 1 to 6 ...
no. 3 example
[0200] A semiconductor memory according to a third embodiment of the present invention will be described below.
[0201] FIG. 17 is a block diagram showing the structure of a semiconductor memory device according to a third embodiment of the present invention. The same reference numerals as in Fig. 12 denote the same components.
[0202] The semiconductor memory of the third embodiment differs from the semiconductor memory of the second embodiment shown in FIG. 12 in that a latch circuit 96 1 to 96 4 Instead of latch circuit 66 1 to 66 4 , and the timing control circuit 135 replaces the timing control circuit 35 .
[0203] In the timing control circuit 135 , an activation timing chain 137 replaces the activation timing chain 37 in the timing control circuit 35 , and a precharge timing chain 136 replaces the precharge timing chain 36 .
[0204] In addition to activating the timing chain 137, it does not output any precharge signal reset signal 14 and sense amplifier enable...
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