Latch structure and latch method

Abstract

The invention provides a latch structure and a latch method.The latch structure comprises an analog-to-digital conversion circuit, a buffer register, an encryption circuit, a first OR gate, a second OR gate, a first trigger and a second trigger, the output end of the encryption circuit is connected with the first OR gate and the second OR gate, the first OR gate is connected with the first trigger, and the second OR gate is connected with the second trigger; the first trigger and the second trigger respectively output an analog signal latch signal and a digital signal latch signal; wherein the analog-to-digital conversion circuit and the buffer register are connected with a first power supply; the encrypted circuit, the first OR gate, the second OR gate, the first trigger and the second trigger are connected with a second power supply which is connected with a capacitor. Based on the scheme, the latch circuit capable of latching the analog signal and the digital signal is realized, and the latch is constructed by an all-digital gate logic, and is small in area overhead and low in power consumption.

Description

technical field [0001] The invention relates to latch technology, in particular to the encrypted latch technology for realizing analog and digital signals. Background technique [0002] A latch is a pulse-level-sensitive memory cell circuit that changes state in response to a specific input pulse level. Latch is to temporarily store the signal to maintain a certain level state. The main function of the latch is to cache, secondly to complete the high-speed control and the out-of-sync problem with the slow peripherals, then to solve the problem of the driver, and finally to solve the problem that an I / O port can both output and input question. [0003] In the prior art, an analog latch must be used to latch an analog signal, resulting in large power consumption and occupying a large chip area; the digital frequency division latch, in the process of power failure, may cause glitches , making the latch fail; [0004] On the other hand, the existing latch has no encryption f...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, an analog latch must be used to latch an analog signal, resulting in large power consumption and occupying a large chip area; the digital frequency division latch, in the process of power failure, may cause glitches , making the latch fail;

[0004] On the other hand, the existing latch has no encryption function; and due to the high power consumption of the existing latch, after the main and auxiliary power supply is powered off, the latched signal is also lost

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