A Miniaturized ldpc Encoder Circuit Based on Code Rate Adaptation

Abstract

The invention discloses a miniaturized LDPC encoder circuit based on code rate self-adaptation, comprising: an encoding core module, a re-encoding network module, and a pipeline trigger group module, wherein the re-encoding network module is used to convert input data into The signal-to-noise ratio data is stripped from the input data; the pipeline trigger group module is used to reduce the path delay between the re-encoding network module and the encoding core module; the encoding core module is used according to the check matrix Numerically computes the input sequence and check matrix over multiple cycles. Through the above methods, the architecture has sufficient advantages in a changeable channel environment. By changing the code rate to reduce the transmission rate, the overall error correction capability can be improved to ensure stable and correct data transmission. At the same time, this LDPC encoder architecture has the characteristics of ultra-miniaturization, extremely low resource utilization and good throughput performance. For some application scenarios that require miniaturization, this architecture has great advantages.

Description

technical field [0001] The invention relates to the field of logic circuits, in particular to a miniaturized LDPC encoder circuit based on code rate adaptation. Background technique [0002] LDPC codes, which have excellent error correction performance and a highly parallel structure. The error correction performance of this channel coding technique is close to the Shannon limit. Although the parity check matrix of the LDPC code has good performance, the problems of the high cost of hardware resources and the large randomness of the matrix in the prior art are not conducive to hardware implementation. Until the QC-LDPC check matrix with quasi-cyclic characteristics was discovered by Tanner, the QC-LDPC check matrix is ​​composed of several cyclic shift sub-matrices, and its regular structure reduces the complexity of VLSI implementation. QC-LDPC code has also become one of the first choices for LDPC code VLSI implementation, and has been adopted by many communication stand...

AI Technical Summary

Problems solved by technology

[0003] But at present, many LDPC encoder circuit architectures are difficult to support the code rate adaptive technology, which will lead to a huge challenge to the error correction capability of the encoder architecture under many complex channel environments. The error correction capability of the encoder architecture is closely related to the stability of the transmission

Secondly, most of the current commercial LDPC encoder architectures use more logic resources, and the throughput is not high enough, which restricts the development needs of miniaturized application scenarios.

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