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Cache optimization method based on RISC processor constant pool layout analysis and integration

A layout analysis and optimization method technology, applied in the direction of electrical digital data processing, instruments, resource allocation, etc., can solve the problems of reducing the cache hit rate, RISC processor performance impact, etc., to reduce the number of cache invalid data and improve the hit rate , the effect of distribution concentration

Pending Publication Date: 2021-08-27
SOUTHEAST UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

These useless but cached data will reduce the hit rate of the Cache and have a certain impact on the performance of the RISC processor

Method used

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  • Cache optimization method based on RISC processor constant pool layout analysis and integration
  • Cache optimization method based on RISC processor constant pool layout analysis and integration
  • Cache optimization method based on RISC processor constant pool layout analysis and integration

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Embodiment 1

[0043] see Figure 1-Figure 8 , this implementation provides a Cache optimization method based on RISC processor constant pool layout analysis and integration, which specifically includes the following steps:

[0044] Step A: using a corresponding compilation tool to obtain an output file in ELF format as the input of the constant pool layout analysis method.

[0045] Step B: Analyze the layout of the constant pool in the program according to the characteristics of the constant pool, specifically including the following steps:

[0046] Step B1: Input the ELF file format obtained in step A, traverse the code segment of the ELF file, find all LDR instructions addressing constants according to the format of LDR instructions addressing constants, and obtain the address and content of LDR instructions.

[0047] Specifically, taking the 32-bit ARM instruction as an example, firstly, by parsing the file in ELF format, find the code segment (.text) of the file, and then traverse the da...

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PUM

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Abstract

The invention discloses a Cache optimization method based on RISC processor constant pool layout analysis and integration. According to the method provided by the invention, layout analysis and integrated optimization of the constant pool of the RISC processor are realized. The method comprises the following steps: by taking an ELF file as input, calculating an address of a corresponding constant by traversing all LDR instructions accessing the constant pool; and traversing all the LDR instructions by constructing two hash tables, deleting constants misjudged as the LDR instructions, and integrating constant pools with continuous addresses to obtain the positions and sizes of all the constant pools. According to the method, the found constant pools are reordered, scattered small constant pools are combined into large constant pools as much as possible, invalid data in the Cache filling process are reduced, and the invalid data comprise constant data loaded into the ICache and instructions loaded into the DCache. Therefore, the missing rate of the Cache is reduced, and the performance of the Cache is improved.

Description

technical field [0001] The invention relates to the technical field of software optimization of a reduced instruction processor, in particular to a Cache optimization method based on layout analysis and integration of a RISC processor constant pool. Background technique [0002] Immediate data is widely used in the instruction set of the processor. Different instruction sets handle immediate data in different ways. The x86-based processor often writes the immediate value directly in the instruction when compiling. The x86 instructions are complex enough to implement register-to-register, immediate-to-register, and memory-to-register assignments. But in RISC processors, there are no such complex instructions. Most RISC instructions are 32-bit or 16-bit. For 32-bit ARM instructions, only 12 bits are used to represent immediate data. Obviously, this can only represent a small part of the immediate value, and cannot represent any 32bits immediate value and address. [0003...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/50
CPCG06F9/3004G06F9/5016G06F2209/5011
Inventor 凌明李红禧
Owner SOUTHEAST UNIV