Data preprocessing method based on AXI bus

Abstract

The invention discloses a data preprocessing method based on an AXI bus. The method comprises the following steps: an arithmetic logic instruction needing to be preprocessed is obtained by a request module; a transmission channel for transmitting a signal ARINST of an operational logic instruction is arranged on the read address channel, and a transmission channel for transmitting a signal RINST is arranged on the read data channel; the signal ARINST is forwarded to the signal RINST after the read request reaches a destination module through a read address channel; a plurality of preprocessing modules are arranged on a data reading channel of an AXI bus; and the signal RINST read data is transmitted to the preprocessing module through the read data channel, the preprocessing module sequentially carries out operation processing on the read data and returns the processed read data to the request module, the preprocessing module preprocesses the read data, the calculation burden of the request module is reduced, and the processing performance of the request module is improved.

Description

technical field [0001] The invention relates to the technical field of large-scale digital integrated circuit design, in particular to an AXI bus-based data preprocessing method. Background technique [0002] As the scale of modern SoC chips increases, the scale of system bus interconnection also increases. At the same time, in order to obtain higher bus bandwidth, the clock frequency of bus operation is also greatly increased. At present, the high-speed interconnection bus commonly used in the industry is a bus system based on the ARMAMBAXI bus protocol. The AXI (Advanced Xtensible Interface) bus protocol is a high-performance, high-bandwidth, low-latency on-chip bus. One of its important advantages is the separation design of address / control and data, so that it can be used on timing-critical paths. A FIFO-like structure registers bus signals, making it easier to obtain timing closure. This FIFO-like registration structure is called AXISlice in the present invention. In...

AI Technical Summary

Problems solved by technology

At the same time, as the applications undertaken by modern SoC chips become more and more complex, processors or hardware accelerators need to spend cycles for precomputation processing to complete complex instructions. At the same time, more frequent memory access requirements also significantly increase the bus transmission time introduced by AXI Slice.

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