Bit line structure, manufacturing method thereof, semiconductor memory and electronic equipment

Abstract

The invention provides a bit line structure, a manufacturing method thereof, a semiconductor memory and electronic equipment. The bit line structure of the present invention includes a semiconductor substrate, and at least one bit line located on the semiconductor substrate; the semiconductor substrate comprises at least one active area limited by a device isolating layer, the bit line is in contact with the active area, and the bit line comprises a metal layer and an insulating layer which are sequentially arranged in an overlapped mode from the semiconductor substrate. According to the bit line structure, a polycrystalline silicon-barrier metal-tungsten structure of the bit line is changed into a metal structure, so that the limitation of the bit line structure under the condition that the size of the bit line structure is smaller than 7nm can be overcome, and after the polycrystalline silicon is removed, further stacking can be carried out.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductors, in particular to a bit line structure, a manufacturing method thereof, a semiconductor memory and electronic equipment. Background technique [0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that typically includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing charge, ie, a bit of information, and a transistor that provides an access signal to the capacitor during read and write operations. The transistor is connected between the bit line and the capacitor, and is gated (turned on or off) by the word line signal. During a read operation, bits of stored information are read from the cell via the associated bit line. During a write operation, a bit of information is stored in the cell from the bit line via the transistor. Cells are dynamic in nature (due to leaks) and...

AI Technical Summary

Problems solved by technology

[0003] The bit line structure of the DRAM using the buried gate structure is below sub-16nm, while the current bit line structure of tungsten-barrier metal-polysilicon structure is below sub-16nm due to the limitation of side wall slope and high aspect ratio There will be great difficulties in the process of

In addition, the physical properties of the polysilicon bit line structure will change when the critical dimension is less than 7nm. This bit line structure has limitations.

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