Unlock instant, AI-driven research and patent intelligence for your innovation.

A chip screening method based on gradient self-verification

A screening method and self-calibration technology, applied in instruments, measuring devices, electronic circuit testing, etc., can solve the problems of low reliability and high cost, and achieve the effects of high reliability, high speed, and restraining interference.

Active Publication Date: 2021-12-10
CHENGDU GANIDE TECH
View PDF12 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem of high cost and low reliability in existing chip screening methods, and proposes a chip screening method based on gradient self-verification

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A chip screening method based on gradient self-verification
  • A chip screening method based on gradient self-verification

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the implementations shown and described in the drawings are only exemplary, intended to explain the principle and spirit of the present invention, rather than limit the scope of the present invention.

[0039] The embodiment of the present invention provides a chip screening method based on gradient self-verification, such as figure 1 As shown, including the following steps S1~S5:

[0040] S1. In the packaging and testing stage of the RF chip to be tested, input seven voltage values ​​​​in sequence at the VDD port of the chip to be tested, keep the remaining ports of the chip to be tested open, and record the output current value corresponding to each input voltage value in turn, and obtain seven an IV value.

[0041] In the embodiment of the present invention, the seven voltage values ​​input at the VDD port of the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a chip screening method based on gradient self-verification, including IV data extraction test, gradient self-verification parameter extraction, ternary self-verification current calculation, ternary difference operation processing, threshold discrimination and chip screening. The present invention finds out abnormal chips with potential defects through formula calculation and data comparison based on the gradient self-verification method. When it is applied in the mass production test stage of the chip, since no new test frequency point and test equipment are introduced, it makes its It has the characteristics of low test cost, high speed and simple configuration environment. In addition, the present invention can significantly restrain the normal fluctuation of chip mass production testing from interfering with mass production testing, effectively intercept abnormal chips with potential defects, thereby reducing the failure rate of chips.

Description

technical field [0001] The invention belongs to the technical field of electronic communication, and in particular relates to the design of a chip screening method based on gradient self-verification. Background technique [0002] The Factory Defective Parts Per Million (FDPPM) requirements of products in the electronic information industry are usually high. How to improve the quality of shipments and reduce the FDPPM of chips is the primary issue for manufacturers to improve profitability and customer satisfaction. One of the main reasons for the high FDPPM is the high early failure rate (Early Failure Rate, EFR) of the chip. Screening out chips that may cause potential failure risks in chip mass production testing is a way to reduce EFR. [0003] Among the current chip screening methods, one is to use the aging test method to work the chip under high temperature and high pressure conditions, so that the logic state of the semiconductor tube will be reversed, and the weake...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
CPCG01R31/2896
Inventor 王测天钟丹邬海峰陈长风胡柳林吕继平黄梦叶珍彭郑童伟
Owner CHENGDU GANIDE TECH