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Chip screening method based on gradient self-checking

A screening method and self-verification technology, applied in the direction of electronic circuit testing, measuring devices, instruments, etc., can solve the problems of high cost and low reliability, and achieve the effect of high speed, high reliability and low subjectivity

Active Publication Date: 2021-10-29
CHENGDU GANIDE TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem of high cost and low reliability in existing chip screening methods, and proposes a chip screening method based on gradient self-verification

Method used

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Embodiment Construction

[0038] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the implementations shown and described in the drawings are only exemplary, intended to explain the principle and spirit of the present invention, rather than limit the scope of the present invention.

[0039] The embodiment of the present invention provides a chip screening method based on gradient self-verification, such as figure 1 As shown, including the following steps S1~S5:

[0040] S1. In the packaging and testing stage of the RF chip to be tested, input seven voltage values ​​​​in sequence at the VDD port of the chip to be tested, keep the remaining ports of the chip to be tested open, and record the output current value corresponding to each input voltage value in turn, and obtain seven an IV value.

[0041] In the embodiment of the present invention, the seven voltage values ​​input at the VDD port of the ...

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Abstract

The invention discloses a chip screening method based on gradient self-checking. The method comprises the steps: IV data extraction testing, gradient self-checking parameter extraction, ternary self-checking current calculation, ternary difference value operation processing, threshold judgment and chip screening. The abnormal chip with potential defects is found out through formula calculation and data comparison based on the gradient self-checking method, and when the method is applied to the mass production test stage of the chip, due to the fact that new test frequency points and test equipment are not introduced, the method has the advantages of being low in test cost, high in speed and simple in configuration environment. Besides, the interference effect of normal fluctuation of a chip mass production test on the mass production test can be remarkably suppressed, and an abnormal chip with potential defects is effectively intercepted, so the fault rate of the chip is reduced.

Description

technical field [0001] The invention belongs to the technical field of electronic communication, and in particular relates to the design of a chip screening method based on gradient self-verification. Background technique [0002] The Factory Defective Parts Per Million (FDPPM) requirements of products in the electronic information industry are usually high. How to improve the quality of shipments and reduce the FDPPM of chips is the primary issue for manufacturers to improve profitability and customer satisfaction. One of the main reasons for the high FDPPM is the high early failure rate (Early Failure Rate, EFR) of the chip. Screening out chips that may cause potential failure risks in chip mass production testing is a way to reduce EFR. [0003] Among the current chip screening methods, one is to use the aging test method to work the chip under high temperature and high pressure conditions, so that the logic state of the semiconductor tube will be reversed, and the weake...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2896
Inventor 王测天钟丹邬海峰陈长风胡柳林吕继平黄梦叶珍彭郑童伟
Owner CHENGDU GANIDE TECH