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Alignment method of patterned wafer and semiconductor equipment

A wafer and pattern technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of low alignment efficiency, waste of target images, and high risk of alignment failure, and achieve improved Alignment Efficiency, Reduced Risk of Alignment Failure, Improved Throughput and Reliability

Active Publication Date: 2021-11-02
SHANGHAI PRECISION MEASUREMENT SEMICON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to disclose a patterned wafer alignment method and semiconductor equipment to solve the problems of low alignment efficiency and waste of collected target images in the patterned wafer alignment process in the prior art and high risk of alignment failure due to improper template selection

Method used

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  • Alignment method of patterned wafer and semiconductor equipment
  • Alignment method of patterned wafer and semiconductor equipment
  • Alignment method of patterned wafer and semiconductor equipment

Examples

Experimental program
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Embodiment 1

[0048] This embodiment discloses a specific implementation of a patterned wafer alignment method (hereinafter referred to as "alignment method"). After the patterned wafer is loaded onto the mechanical motion platform (in the embodiment, the mechanical motion platform 115 hereinafter), the patterned wafer is aligned using this alignment method.

[0049] Such as figure 1 As shown, the semiconductor device 100 uses the alignment method disclosed in this embodiment to perform an alignment operation on a wafer. The semiconductor equipment 100 includes the most basic front-end mechanical module (Equipment Front End Module, EFEM) 110 for wafer loading and unloading, which can place a wafer box 112 (FOUP), and the front-end mechanical module 110 has wafer pre-alignment A device 113 and a robot arm 114, the pre-aligner 113 is used for pre-aligning the wafer, and the robot arm 114 is used for loading and unloading wafers. The semiconductor device 100 also includes a mechanical movem...

Embodiment 2

[0120] ginseng figure 1 As shown, this embodiment discloses a semiconductor device 100 .

[0121] The semiconductor device 100 uses the patterned wafer alignment method described in the first embodiment to perform an alignment operation on the wafer. The semiconductor device 100 is a VLSI manufacturing device or a defect inspection device. This embodiment has the same part of the technical solutions as in the first embodiment, refer to the description in the first embodiment, and will not repeat them here.

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Abstract

The invention provides an alignment method for a patterned wafer and semiconductor equipment. The method comprises the steps: collecting a basic template image when a menu is created, and collecting a plurality of adjacent template images in an area adjacent to an image collection area of the basic template image so as to form a spliced template image; extracting a basic forward template containing features from the basic template image, and storing the basic forward template to a menu; when the menu is executed, carrying out forward matching and / or reverse matching to obtain a first matching point with a patterned wafer, executing forward matching according to a basic forward template and an acquired target image, extracting a reverse template containing features according to the target image, and executing reverse matching according to the reverse template and a spliced template image; and after the first matching point is obtained, obtaining other matching points, and carrying out the level alignment of the patterned wafer according to the first matching point and the other matching points. According to the invention, the alignment efficiency of the patterned wafer is improved, and the risk of alignment failure is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor equipment, in particular to an alignment method of a patterned wafer and semiconductor equipment. Background technique [0002] Large-scale integrated circuit manufacturing and testing equipment is referred to as semiconductor equipment. In order to ensure its working accuracy, it is necessary to perform wafer alignment after loading a patterned wafer (Patterned Wafer). [0003] The work of semiconductor equipment includes two parts: creating menu and executing menu. Such as Figure 2 to Figure 4 As shown, when creating a menu for wafer alignment, it is common to select features in template images 210 / 310 / 410 (eg, Figure 4 Features in 412, figure 2 and image 3 The area not marked in ) is used as the template 211 / 311 / 411, and the template 211 / 311 / 411 is required to be unique in the template image 210 / 310 / 410, and the brightness and contrast must meet the established requirements, and th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/68H01L23/544
CPCH01L21/682H01L23/544H01L2223/54426
Inventor 刘骊松
Owner SHANGHAI PRECISION MEASUREMENT SEMICON TECH INC