Semiconductor packaging structure and manufacturing method thereof
A packaging structure and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as difficulty in reducing the overall size, enlarging the size of the package, and elongating the electrical path
Pending Publication Date: 2021-11-02
ADVANCED SEMICON ENG INC
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Problems solved by technology
like figure 1 The existing stacked packaging structure shown not only increases the process complexity and manufacturing cost, but also makes the packaged The size becomes larger, and the electrical path becomes longer, resulting in higher impedance
In addition, a thicker (Thickness>0.2mm) existing substrate 12 and longer wires are required to realize electrical signal transmission between chips, and it is difficult to reduce the overall size of the existing stacked packaging structure, which hinders the development of semiconductor devices. Package Miniaturization
Method used
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[0040] The specific implementation manners of the present disclosure will be described below in conjunction with the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced through the contents recorded in this specification. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. In addition, for the convenience of description, only the parts related to the related invention are shown in the drawings.
[0041] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the specification are only used to match the content recorded in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present disclosure. There are limited conditions, so it has...
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According to a semiconductor packaging structure and a manufacturing method thereof provided by the invention, a first stacked chip group and a second stacked chip group are stacked up and down through an electric connecting piece (such as the conductive column), and the electric connection is realized. The first stacked chip group and the second stacked chip group are stacked up and down so that gaps between parallel stacks of the stacked chip groups in an existing stacked packaging structure do not exist, and a through silicon via (TSV) or other via hole mode does not need to be used and a rewiring layer does not need to be matched. The electric path is shortened; and the overall size of the stacked packaging structure is reduced.
Description
technical field [0001] The present disclosure relates to the field of semiconductor technology, in particular to a semiconductor package structure and a manufacturing method thereof. Background technique [0002] With the continuous upgrading of electronic products, there is an increasing demand for storage architectures with higher digital information processing efficiency, higher storage capacity and flexibility. To meet this demand, stacked packaging technology is developing rapidly. [0003] In order to realize the requirement of large capacity, the number of integrated chips (such as memory chips) is increasing day by day. like figure 1 The existing stacked packaging structure shown not only increases the process complexity and manufacturing cost, but also makes the packaged The size becomes larger, and the electrical path becomes longer resulting in higher impedance. In addition, a thicker (Thickness>0.2mm) existing substrate 12 and longer wires are required to rea...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L25/065H01L21/50H01L21/56
CPCH01L25/0657H01L21/50H01L21/56H01L2225/06506H01L2225/0651H01L2225/06513H01L2225/06517H01L2225/06527H01L2225/06568
Inventor 吕文隆
Owner ADVANCED SEMICON ENG INC