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Isolated NLDMOS device and manufacturing method thereof

A manufacturing method and isolation-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of reducing the P-type well 204P-type net doping concentration, reducing the depletion capability of the drift region, and reducing device breakdown. voltage and other issues, to achieve good isolation effect, enhance depletion capability, and improve the effect of breakdown voltage

Pending Publication Date: 2021-11-05
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

figure 1 In the existing structure shown, the second deep well ion implantation region 202b directly surrounds the P-type well 204, which will reduce the P-type net doping concentration of the P-type well 204, that is, will make the drift region The concentration relative to the P-type well 204 will be relatively thick, thereby reducing the depletion ability of the drift region, and finally reducing the breakdown voltage of the device

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  • Isolated NLDMOS device and manufacturing method thereof
  • Isolated NLDMOS device and manufacturing method thereof
  • Isolated NLDMOS device and manufacturing method thereof

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Embodiment Construction

[0072] Such as figure 2 As shown, it is a schematic structural diagram of the isolated PLDMOS device of the embodiment of the present invention; in the isolated NLDMOS device of the embodiment of the present invention, an N-type doped first deep well ion implantation region 102a is formed on the P-type semiconductor substrate 101 and a plurality of N-type doped second deep well ion implantation regions 102 b and P-type wells 104 .

[0073] The source region 107 a composed of N+ regions is formed on the surface of the P-type well 104 .

[0074] A drain region 107b composed of an N+ region is formed on the surface of the first deep well ion implantation region 102a.

[0075] A gate structure is formed on the surface of the P-type well 104, the gate structure is composed of a gate dielectric layer 105 and a polysilicon gate 106, and the source region 107a and the first side of the gate structure are formed from alignment.

[0076] There is a first distance between the first d...

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Abstract

The invention discloses an isolated NLDMOS device. A first deep trap ion implantation region, a plurality of second deep trap ion implantation regions and a P-type trap are formed on a P-type semiconductor substrate; a first space is formed between the first deep trap ion implantation region and a second deep trap ion implantation region closest to a drain region; the first deep trap ion implantation region and each second deep trap ion implantation region are integrally communicated after thermal propulsion and form an N-type deep trap; the N-type deep well between the second side surface of the P-type well and the drain region forms a drift region; a second space is formed between the second deep trap ion implantation regions, and the P-type trap is surrounded by an integral structure formed by the second deep trap ion implantation regions; and by setting the second space, the influence of the N-type deep well on the P-type concentration of the P-type trap is reduced, and the P-type net doping concentration of the P-type trap is increased. The invention further discloses a manufacturing method of the isolation type NLDMOS device. According to the invention, the breakdown voltage of the device can be improved, and meanwhile, a good isolation effect between the body region and the semiconductor substrate is ensured.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to an isolated NLDMOS device; the invention also relates to a manufacturing method of the isolated NLDMOS device. Background technique [0002] In conventional non-isolated NLDMOS, there is no isolation structure between the body region (body) composed of P-type wells and the P-type semiconductor substrate, so that the body region and the source region composed of N+ regions formed in the body region can only be connected to the same potential as the semiconductor substrate, that is, 0V potential. NLDMOS means N-type LDMOS. [0003] N-type deep well isolation is used between the body region of the isolated NLDMOS and the P-type semiconductor substrate, so that the body region and the source region can be connected to a voltage different from that of the semiconductor substrate, so that the body region and the source region can be at 0V potential and F...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L21/336
CPCH01L29/0611H01L29/7816H01L29/66681
Inventor 段文婷刘冬华
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP