Isolated NLDMOS device and manufacturing method thereof
A manufacturing method and isolation-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of reducing the P-type well 204P-type net doping concentration, reducing the depletion capability of the drift region, and reducing device breakdown. voltage and other issues, to achieve good isolation effect, enhance depletion capability, and improve the effect of breakdown voltage
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[0072] Such as figure 2 As shown, it is a schematic structural diagram of the isolated PLDMOS device of the embodiment of the present invention; in the isolated NLDMOS device of the embodiment of the present invention, an N-type doped first deep well ion implantation region 102a is formed on the P-type semiconductor substrate 101 and a plurality of N-type doped second deep well ion implantation regions 102 b and P-type wells 104 .
[0073] The source region 107 a composed of N+ regions is formed on the surface of the P-type well 104 .
[0074] A drain region 107b composed of an N+ region is formed on the surface of the first deep well ion implantation region 102a.
[0075] A gate structure is formed on the surface of the P-type well 104, the gate structure is composed of a gate dielectric layer 105 and a polysilicon gate 106, and the source region 107a and the first side of the gate structure are formed from alignment.
[0076] There is a first distance between the first d...
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