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A method of board-level packaging

A board-level and package technology, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of large height difference between chips and pads, high requirements for chip pads, and difficult mounting, and achieve cross-sectional area Large size, low pad property requirements, and good electrical conductivity

Active Publication Date: 2022-02-08
华宇华源电子科技(深圳)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to solve the existing method of lead-out of chip electrodes. There is a method of laser drilling blind holes + sinking copper electroplating with high cost, high requirements for chip pads, and large limitations. The bump process method has high cost and is difficult to mount. Large, the cost of the CuClip process is high, and the problem that it cannot be processed when the height difference between the chip and the pad is large

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0062] Such as Figures 1 to 9 Shown: A method of board-level packaging, follow the steps below:

[0063] Step 1, prepare a peelable first carrier 10;

[0064] The first carrier 10 comprises a rigid first carrier 11, a first conductive metal layer 12, a first adhesive layer 13, and the first adhesive layer 13 is used to connect the first conductive metal layer 12 to the first The carrier boards 11 are temporarily glued together;

[0065] Step 2, prepare a peelable second carrier 20;

[0066] The second carrier 20 includes a rigid second carrier 21, a second conductive metal layer 22, a second adhesive layer 23, and the second adhesive layer 23 is used to connect the second conductive metal layer 22 to the second The carrier boards 21 are temporarily glued together;

[0067] Step 3: Paste a layer of photosensitive film on the first conductive metal layer 12 of the first carrier 10, and form at least two isolated pads 14 (that is, electroplating pads) on the first carrier 10...

Embodiment 2

[0084] Such as Figure 10 As shown, the difference from Embodiment 1 is that the method for forming the connector in step 5 is: on the surface of the second conductive metal layer 22 of the second carrier 20, at least two copper strips 25 of different heights are welded, and the copper strips The height difference of 25 is equal to the thickness of chip 30 . The rest of the content is exactly the same as that of Embodiment 1, and will not be repeated here.

Embodiment 3

[0086] Such as Figures 11 to 14 As shown, the difference from Embodiment 1 is that the chip 30 in Embodiment 1 has an upper pin and one lower pin respectively, and the chip 30 in Embodiment 3 has one pin on the bottom and two pins 31 on the top. Ground, three pads 14 are provided on the first carrier 10, and four connectors are provided on the second carrier 20 (for example, four pads 14 and two thickened electroplated pads 24 are provided). Accordingly, the package The lower part of 100 is provided with three external pads 101 as pins of the device. The rest of the content is completely the same (or similar in principle) to Embodiment 1, and will not be repeated here.

[0087] In summary, adopting the technical solution of the present invention has the following beneficial effects:

[0088] The present invention solves the problem of the existing lead-out method of chip electrodes. The method of laser drilling blind holes + sinking copper electroplating has high cost, high...

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Abstract

The invention relates to a method for board-level packaging. Step 1, prepare a peelable first carrier; Step 2, prepare a peelable second carrier; Step 3, paste the first conductive metal layer on the first carrier A layer of photosensitive film, forming at least two isolated pads on the first carrier by means of graphics and electroplating; step 4, mounting and welding at least one chip on a pad of the first carrier; step 5, Generate at least two connectors on the surface of the second conductive metal layer of the second carrier for soldering, wherein the height of at least one connector matches the thickness of the chip; step 6, use a pressing sheet to place on the corresponding chip Open a window at the position of the pad and pad; step 7, apply solder on the chip of the first carrier and another pad; step 8, cover the chip and pad of the first carrier with a bonding sheet. The connection body is pressed together by the pressing sheet, and then soldered to form a package body.

Description

technical field [0001] The invention relates to the technical field of chip board-level packaging, in particular to a board-level packaging method. Background technique [0002] In the existing process flow of panel level packaging, there are the following defects in the lead-out method of chip electrodes: [0003] (1) For the method of laser drilling blind holes + immersion copper plating, the main problems are high cost (laser drilling equipment is more expensive), and high requirements for chip pads (general materials cannot withstand laser lasers and are easily damaged) , Large limitations. [0004] (2) Bump (value ball) process method, the main problem is that first of all, the cost of bumping the chip is high, and it is difficult to mount the chip after bumping; it is required that the chip and the pads to be interconnected with it must have the same height. It is difficult to realize; [0005] (3) Cu Clip (copper sheet) process method, first of all, the production ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/56H01L21/60
CPCH01L21/50H01L21/568H01L24/81H01L24/89H01L2224/91
Inventor 邓榕秀梁万里
Owner 华宇华源电子科技(深圳)有限公司
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