Low power apparatus and method to multiply frequency of a clock

Abstract

Disclosed are a low power apparatus and method to multiply frequency of a clock. A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32*, 4*, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL / MDLL, higher bandwidth for the PLL / MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Description

technical field [0001] The present disclosure relates to low power devices and methods for clock multiplication. Background technique [0002] An external crystal (XTAL) provides the root reference clock frequency for the processor's phase-locked loop (PLL). Due to power consumption, phase noise and cost considerations, the reference clock frequency is usually limited to no more than 100MHz. 38.4MHz off-die XTAL is widely accepted on many computer platforms. For any PLL of the processor, its input reference clock frequency (f REF ) to set its maximum stable loop bandwidth (approximately f REF 10% of The higher the PLL bandwidth, the shorter the settling and / or lock time and the lower the long-term PLL output clock jitter. However, low root reference clock frequency results in lower PLL bandwidth. A lower PLL bandwidth filters out less PLL oscillator noise and increases PLL lock and / or settling time. For a given PLL output frequency, low f REF The feedback divider rat...

AI Technical Summary

Problems solved by technology

For a given PLL output frequency, low f REF The feedback divider ratio (N) is increased, thereby 1) increasing the phase-frequency detector (PFD) and charge pump noise of the PLL, and 2) due to the delta-sigma modulator in the fractional-N mode of the divider ( delta-sigma modulator), which increases the quantization noise of the PLL divider

A lower f REF also results in higher loop filter capacitance and its layout area

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