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In-memory operation method and device and application thereof

A computing method and technology of computing units, which are applied to in-memory computing, devices and their application fields, can solve the problems that computing results are easily affected by noise, area waste, etc., so as to increase the cost of circuit area, ensure high efficiency, and high computing energy efficiency. Effect

Pending Publication Date: 2021-11-19
HEFEI HENGSHUO SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to make calculations happen at the same time, this scheme has high calculation performance, but because other channels need to be set to 0 during calculation, no current response is generated for any input, that is, no information can be stored, so it has a large area. waste
[0005] In addition, since the in-memory calculation uses the analog domain characteristics of the memory for calculation, the calculation result is easily affected by noise

Method used

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  • In-memory operation method and device and application thereof

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Embodiment 1

[0086] Please refer to Figure 1-6 , an in-memory computing method of this embodiment, comprising:

[0087] The storage array is divided and configured into several basic operation blocks according to the single-channel operation function. The storage array can be one of NOR Flash storage array, ReRAM storage array, SRAM storage array or DRAM storage array. As for which storage array to choose for implementation The structure of the computing unit of the present invention is all all can, and technician can select according to need, therefore in this embodiment take NOR Flash storage array as example to carry out further introduction;

[0088] The output terminals of all the operation units in the operation basic block are connected to the matching local summation line LSL, such as figure 1 As shown, in this embodiment, the operation unit is a single storage unit, and a single storage unit is also a single floating gate field effect transistor such as figure 2 As shown, the ...

Embodiment 2

[0101] An in-memory computing method in this embodiment is similar to the in-memory method in embodiment 1, the main difference is that the composition of the computing unit is different, so the similarities in this embodiment and embodiment 1 will not be repeated, please refer to the embodiment Contents in 1;

[0102] An in-memory computing method provided in this embodiment includes:

[0103] The storage array is divided and configured into several computing basic blocks according to the single-channel operation function, wherein the storage array can be one of a NOR Flash storage array, a ReRAM storage array, an SRAM storage array or a DRAM storage array, and in this embodiment, the NOR The Flash storage array is taken as an example for further introduction;

[0104] Connect the output terminals of all the operation units in the operation basic block to the matching local summation line LSL, please refer to Figure 7 , in this embodiment, the operation unit is a combinati...

Embodiment 3

[0122] Please refer to Figure 12 , this embodiment provides an in-memory computing device, which is set to match the in-memory computing method in Embodiment 1, so some of the same content in this embodiment is the same as in Implementation 1, please refer to Embodiment 1, The in-memory operation device of this embodiment includes an operation array, an input module, a DAC module, a clock module, an SEL control module, a controller module, an ADC module and a shift selection module arranged in cooperation with each other;

[0123] The operation array is composed of several operation basic blocks, summation line LSL, summation line GSL and controlled switches, wherein the output terminals of all operation units in the operation basic block are connected to the local summation line LSL in a normalized manner, and each of the operation units located in the same column The summation line LSL is respectively connected to the summation line GSL data set by column through the contro...

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Abstract

The invention relates to the technical field of memories, and discloses an in-memory operation method and device and application thereof. The method comprises the steps: dividing and configuring a storage array into a plurality of operation basic blocks according to a single-channel operation function, normalizing the output ends of all operation units in the operation basic blocks to be connected into matched local summing lines LSL, and arranging summing lines GSL according to columns, wherein each matching operation basic block is provided with a controlled switch; enabling each summing line LSL located on the same column to be in data connection with a summing line GSL through the controlled switch, configuring parameters of the operation basic blocks, reading the data to be operated, selectively switching on or off the controlled switches, and outputting the target operation result data in cooperation with output shifting operation. According to the method, in-memory calculation including grouping convolution can be more efficiently realized, higher calculation performance and a more excellent calculation energy efficiency ratio are achieved, the correctness of overall calculation is ensured, and the practical value in practical significance is achieved.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to an in-memory computing method, device and application thereof. Background technique [0002] In-memory computing is widely used in the acceleration of matrix operations in artificial intelligence, such as vector matrix multiplication and high-dimensional convolution operations. However, with the development of artificial intelligence algorithms, lightweight algorithms have begun to gain more attention, and the convolutional neural network has gradually changed from traditional convolution to lighter convolution. The most common way is group convolution or convolution. Depthwise separable convolution. However, the existing in-memory computing has weak support for this kind of lightweight convolution, and it is difficult to take advantage of the memory computing. [0003] For example, in an existing traditional method, when calculating the grouped convolution, the weight matrix i...

Claims

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Application Information

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IPC IPC(8): G06F17/15G06F17/16G11C16/04G11C13/00G11C11/401G11C11/412
CPCG06F17/15G06F17/16G11C16/0483G11C13/0002G11C11/401G11C11/412
Inventor 盛荣华陶临风李政达吕向东任军陈真欧阳托日唐伟童
Owner HEFEI HENGSHUO SEMICON CO LTD
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