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Wafer test board, wafer test system and wafer test method

A chip testing, chip technology, applied in the direction of semiconductor/solid-state device testing/measurement, single semiconductor device testing, electrical measurement, etc., can solve problems affecting signal integrity, capacitive and inductive interference, etc., to maintain integrity, The effect of simple and compact structure

Active Publication Date: 2021-11-23
APLUS SEMICON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] For this reason, the present invention proposes a chip test board, which can solve the problem that the signal integrity of the signal is affected by capacitive and inductive interference due to the use of via hole testing when the chip signal is tested.

Method used

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  • Wafer test board, wafer test system and wafer test method
  • Wafer test board, wafer test system and wafer test method
  • Wafer test board, wafer test system and wafer test method

Examples

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Embodiment Construction

[0030] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0031] In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial" , "radial", "circumferential" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present ...

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Abstract

The invention discloses a wafer test board, which is used for testing a wafer according to a primary signal and a secondary signal, and comprises a body provided with a plurality of first through holes communicated with the two sides of the body; a wafer testing area which is arranged on one side of the body; and a main signal connector which is arranged on the same side of the body and is used for being connected with the wafer testing area without passing through the first through holes; wherein the wafer testing area is used for connecting a wafer and testing at least one main signal of the wafer through the main signal connector.

Description

technical field [0001] The invention belongs to the technical field of wafer testing, and in particular relates to a wafer testing board, a testing system and a testing method. Background technique [0002] Existing LCD mobile phone display driver chips, or display screens for wearable watches, and large-size TV display driver chips, these design factories and test factories test the single chip (display driver chip) in order to test the electrical properties of the single chip Or analysis, it will be pulled from the output terminal or input terminal on the chip to the test point of the chip test board by means of pulling wires, and connected to the user's test environment through the vias (Via) around the test board. , so when the signal is transmitted, such a via design will have capacitive and inductive effects on the signal, which will affect the integrity of the high-speed signal. Furthermore, the COB (chip on board) design of the existing driver IC chip is designed to...

Claims

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Application Information

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IPC IPC(8): G01R31/26G01R1/02H01L21/66
CPCG01R31/2601G01R1/02H01L22/30
Inventor 蔡水河赖政忠
Owner APLUS SEMICON TECH CO LTD
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