Quick memory data reading method

A memory and memory address technology, applied in the direction of electrical digital data processing, input/output process of data processing, instruments, etc., to achieve the effect of saving operation time, good reusability, and reducing memory operation time

Active Publication Date: 2021-11-23
TIANJIN JINHANG COMP TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These factors limit the minimum time of the read cycle, that is, the read speed of the APB interface for the memory

Method used

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Examples

Experimental program
Comparison scheme
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Embodiment 1

[0062] SUMMARY Example embodiments of the present invention is detailed in terms of data transmission.

[0063] 1, the interface aspects of the system, connected to a conventional way, both the exchange data between the processor and memory via the bus interface through the APB bus APB; the present invention increases the pretreatment and the branch judgment mechanism, the processor module address signal, a read signal is processed to the memory, not through the APB bus.

[0064] 2, the mechanism of speed, through the pre-determination module and the branch address signals and write signals leads directly from the processor, will read and write address signals to the memory bus APB stage at T1, so that the memory data begins operation, T2 cycle data will be sent to the APB bus ready, to avoid waiting for a case where the memory bus for processing data appears.

[0065] 3, the process speed operation, divided into the following processes (a processor to read a complete example):

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PUM

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Abstract

The invention belongs to the technical field of computer storage, and particularly relates to a quick memory data reading method. The quick memory data reading method is implemented based on the quick memory data reading system. The quick memory data reading system comprises a processor, an APB bus module, a memory and a preprocessing module. According to the characteristics of an APB bus interface access mechanism, a pre-reading mechanism and a branch judgment mechanism are utilized to realize command sending and data reading in advance for the memory, so that the waiting time of data sending out of the APB bus interface is shortened, the data reading speed is improved, the compatibility, usability and maintainability of a system are kept. The quick memory data reading method has very important application significance.

Description

Technical field [0001] The present invention belongs to the field of computer storage technology, particularly, to a rapid method for reading memory data. Background technique [0002] Embedded systems are currently widely used or an ASIC chip on the memory data bus APB access, via commands sent APB bus, the data latched in the data read operation, since the presence of a case where the memory data interface itself delay, APB bus interface present data for the memory access speed a certain limit, in some memory for the data read speed is relatively high usage conditions can not meet the demand. [0003] Specifically, for a typical architecture model APB memory interface, such as its connection relationship Picture 1-1 Indicated. [0004] Picture 1-1 Conventional listed APB bus interface connection, in a conventional manner APB bus interface, the processor bus access memory chips through the APB. APB bus by the processor and the address signal ADDR, DATA data signals, SEL and chi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F13/16G06F13/40
CPCG06F3/0611G06F3/0638G06F13/1684G06F13/4004
Inventor 李鑫朱天成曾永红李岩刘慧婕
Owner TIANJIN JINHANG COMP TECH RES INST
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