Configurable parallel processing transposition preprocessing module

Abstract

The invention relates to a configurable parallel processing transposition preprocessing module, which comprises an input end, an output end, a 1-to-N logic unit, a row and column transpose logic unit and an N-to-1 logic unit, the input end is connected with the 1-to-N logic unit, the 1-to-N logic unit is connected with the row and column transpose logic unit, the row and column transpose logic unit is connected with the N-to-1 logic unit, the N-to-1 logic unit is connected with the output end, the input end and the output end both adopt AXI Stream standard interfaces, the bit width is 256 bits, the embedded software configures the value of a register through an APB bus, and the 1-to-N logic unit or the N-to-1 logic unit is selected for operation through bypass. The configurable parallel processing transposition preprocessing module has the advantages that: 1-to-N conversion and N-to-1 conversion can be realized for the data format, so that multi-line operation can be conveniently realized by algorithms such as FFT and the like at one time, and the configurable parallel processing transposition preprocessing module has flexibility and universality; and the data extraction logic unit is combined with the transpose logic unit, and a bypass selection design is set, so that different function selections can be carried out, and the timeliness of the system is improved.

Description

technical field [0001] The invention belongs to the technical field of image data processing, and in particular relates to a configurable parallel processing transposition preprocessing module. Background technique [0002] With the continuous progress in the field of image data processing, the signal processing algorithms used are becoming more and more advanced, and the data processing methods have become more complex. In order to efficiently complete the processing of various algorithms, only the FPGA solution is used. Although its operation speed is fast, but Due to the limited memory capacity of its own storage unit MEM, when dealing with large-scale data streams in large-scale projects, insufficient memory cannot meet the demand for data volume. [0003] DDR SDRAM has a large memory and has high-speed read and write functions, but the image processing algorithm sometimes needs to change the way of data extraction, and operations such as cross-row, multi-row, and multi-...

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Problems solved by technology

[0002] With the continuous progress in the field of image data processing, the signal processing algorithms used are becoming more and more advanced, and the data processing methods have become more complex. In order to efficiently complete the processing of various algorithms, only the FPGA solution is used. Although its operation speed is fast, but Due to the limited memory capacity of its own storage unit MEM, when dealing with large-scale data streams in large-scale projects, insufficient memory cannot meet the demand for data volume

[0003] DDR SDRAM has a large memory and has high-speed read and write functions, but the image processing algorithm sometimes needs to change the way of data extraction, and operations such as cross-row, multi-row, and multi-column operations are used, which makes DDR read and write data less efficient and resource-intensive. The utilization rate is low, so the problem of efficient processing of complex algorithms with a large amount of data needs to be improved and solved

The existing FPGA+DDR solution has fast parallel processing speed of FPGA, large external DDR storage, and high reading and writing speed triggered by both edges. In the image data processing system, there is conversion between distance direction and azimuth direction. The azimuth direction is the column direction, so the function of transposition is needed to facilitate the effective processing and operation of data by FFT and other algorithms. In DDR, data is stored in Bank blocks, and a Bank block is divided into row operations and column operations. For distance direction The reading is transferred to the writing in the azimuth direction. The existing technology is to design the transposition module to move the data from the DDR line by line and write it into another DDR line by line through the transposition module, so that the distance direction and the azimuth direction are realized. Due to the huge amount of data, each row operation needs to perform an address jump operation, which will reduce the processing efficiency of the system

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