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Neural network regularization bit serial calculation compression method and device

A neural network and serial computing technology, applied in neural learning methods, biological neural network models, computing, etc., can solve problems such as uneven distribution of bit sparsity and unbalanced load of computing units, so as to improve computing power and reduce power consumption. energy consumption and improve energy efficiency

Pending Publication Date: 2022-01-07
GUIZHOU POWER GRID CO LTD +1
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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a compression method and device for neural network regularized bit-serial calculation, to solve the problem that although the bit-serial accelerator in the prior art can improve the weight bit sparsity, the bit sparsity is lower than the weight value. The distribution in is still uneven, and there is also the problem of unbalanced load on the computing units in the accelerator.

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  • Neural network regularization bit serial calculation compression method and device
  • Neural network regularization bit serial calculation compression method and device
  • Neural network regularization bit serial calculation compression method and device

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[0032] Because the existing serial accelerator can reduce the operation by skipping the operation which is 0 in the bit stream. Therefore, improving the bit sparsity in the neural network model, that is, the ratio of 0 in the weight binary can improve the efficiency of network operations. However, it is not enough to improve the network bit sparsity, and there is also the problem of uneven distribution of sparsity. For example, when multiple sets of data are simultaneously operated on the serial operation unit, the operation time of each set of data is different due to the number of 1 bits contained in each set is different. In order to ensure the synchronization between each group of computing units, the accelerator will force the group that completes first to wait for the group that completes later until all operations are completed before jumping to the next batch of data. Such a mechanism will lead to a great waste of resources.

[0033] The method of the present inventi...

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Abstract

The invention discloses a compression method for neural network regularization bit serial calculation. The compression method comprises the following steps: 1, quantizing a weight and an activation value in a trained full-precision neural network model; 2, performing bit sparse training with guidance on the quantized neural network model; 3, performing group structured constraint training on the neural network model subjected to bit sparse training to solve the problem of non-uniform distribution of non-zero bits in weights; 4, deploying the trained neural network model to a neural network accelerator with a structured bit serial multiplication component. Therefore, the problems that although a bit serial accelerator in the prior art can improve the weight bit sparseness, the distribution of the bit sparseness in the weight is still nonuniform, and the load of an arithmetic unit in the accelerator is unbalanced are solved.

Description

technical field [0001] The invention relates to the technical field of embedded data intelligent processing and artificial intelligence; in particular, it relates to a compression method and device for neural network regularized bit serial calculation. Background technique [0002] At present, neural network has become a powerful algorithm in artificial intelligence, computer vision and other fields, and the applications involved are becoming more and more extensive. However, the neural network has a huge demand for computing power and storage space, which makes it very challenging to carry it on various edge devices or embedded devices with limited performance and power consumption. Therefore, various neural network accelerator technologies have been born. [0003] The bit-serial neural network accelerator replaces the parallel multiplier in the traditional neural network accelerator with an AND gate, a shifter and an adder, and performs a 1-bit multiply-accumulate operati...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/08G06N3/04G06F7/525G06F7/544
CPCG06N3/063G06N3/084G06F7/525G06F7/5443G06N3/045
Inventor 徐长宝辛明勇高吉普王宇刘卓毅张历习伟姚浩陈军健于杨陶伟
Owner GUIZHOU POWER GRID CO LTD