[0018] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following examples are intended to illustrate the invention, but not to limit the scope of the invention.
[0019] Please refer to figure 1 , Embodiments provide a PLED driver chip according to the present invention, includes a substrate 10, VDD (DeviceVoltage, positive voltage chips) interface 20, GND (Ground, a negative voltage chips) interface 30, an interface signal line 40, external to VDD line 50, the external GND wiring 60, wiring 70 and the external signal line GND terminal head (not shown). GND end located within the substrate 10, interface 20 VDD, GND terminal 30, the interface signal lines 40 are disposed on the outer surface of the substrate 10, external VDD wiring 50 and the interface 20 is connected to VDD, GND wiring 60 is connected to the external interface 30 GND .
[0020] Interface 20 VDD, GND terminal 30 and a signal line arranged in a line interface 40, the interface 40 located between the signal line 20 and the GND terminal 30 interfaces VDD. With respect to the conventional drive chip, VDD functions the interface 20, GND interface 30 and the interface 40 signal lines arranged sequentially embodiment, the connection pin in the middle there is not enough space, resulting in a large impedance. In this embodiment, the interface 20 and the VDD GND terminal ends 30 disposed in the signal line interface 40 of the interface 20 and the GND VDD interface 30 has sufficient space set width power connection, reducing the impedance of the power connection, thereby reducing the loop pressure drop, reducing the PLED display luminance is reduced while reducing the heat loss of power, more efficient use of the battery.
[0021] Also known as film resistor sheet resistance, referred to as sheet resistance, the film is applied to the film units, it means a square conductive material film between the side edges to the resistor. Any size squares edge to edge resistance is the same, regardless of the side length of 1 m or 0.1 m, the sheet resistance thereof is the same, i.e. only the sheet resistance factors related to the thickness of the conductive film. Equation sheet resistance of Rs = ρ / t (ρ is the resistivity of the block material, t is the thickness of the block material) can be seen, when the bulk resistance calculated, using the sheet resistance can be obtained by the aspect ratio, the equation of R = Rs * L / W (L is the block length of material, i.e., the connection length, W is the width of the bulk material, i.e. the width of the connection).
[0022] Since VDD interfaces 20, GND interface 30 has sufficient space arrangement, wider connections may be provided, as far as possible close to the width dimension of the connection length, so that L / W becomes smaller size, to reduce the power connection impedance. External VDD wiring 50 comprises a first long side 51 and a second long side 51 perpendicular to the first broad side 52, 52 is connected to a first broadside PLED driver chip, a first long side 51 and the PLED driver chip is flush . GND connection 60 includes a second outer broadside second long side 61 and a second long side 61 of the vertical 62, and a second broadside PLED driver chip 62 is connected, and a second long side 61 of the PLED driver chip is flush . 50 by an external wiring VDD, GND external wiring 60 and a long side edge flush PLED driver chip, the greatest degree of improved external VDD wiring 50, the external width dimension 60. The GND connections.
[0023] In the present embodiment, the outer length and width equal to VDD wiring 50 and the external GND wiring 60 is equal to the length and width. External VDD wiring 50, the external aspect ratio GND wiring 60 are a minimum. External wiring 50 is assumed VDD, GND external connection wires 60 used for the sheet resistance 12Ω / □ , PLED driver chip operating current is 10mA, the present embodiment is the external VDD wiring 50 in the embodiment, resistance of the external GND wiring 60 are 12 [Omega], the impedance of the voltage drop ITO
[0024] (12Ω + 12Ω) * 10mA = 0.24V
[0025] Conventional PLED driver chip, an external connection 50 VDD, GND external wiring trace 60 long and slender, generally an aspect ratio greater than 4, i.e. a resistance greater than 48Ω, the impedance voltage drop of at least ITO
[0026] (48Ω + 48Ω) * 10mA = 0.96V
[0027] Values can be seen, the present embodiment of the impedance voltage drop ITO embodiment is much smaller than conventional schemes, thereby reducing the loop pressure drop, reducing the PLED display brightness reduction.
[0028] Interface 20 includes a plurality of VDD VDD pin 21, it is located on the same side of the interface signal lines 40, 21 connect all the VDD pin 50 and the external VDD is connected by soldering. Interface 30 includes a plurality of GND GND pin 31, it is located on the same side of the interface signal lines 40, 31 connect all the GND pins 60 and the external GND are connected by soldering.
[0029] On the positive and negative wire resistance, the greater the number of pins, the smaller the impedance. However, multiple number of pins, the number of the welding head also, high production costs and low productivity. Embodiment, VDD 21 and GND pin is equal to the number of pins 31 number, are three in the present embodiment. By providing a plurality of pins VDD 21 and GND pin 31, to further reduce the wire resistance of the power supply at the same time, without excessive increase in production cost.
[0030] External signal line connecting the signal line 70 by the number of the interface 40 the number of pins and the same correspondence, are connected by soldering.
[0031] GND is a power supply circuit chip signal, all currents flow through the GND, the chip inside the metal trace impedance is not too large. GND interface 30 of the present embodiment by the multi-layer metal wire and the GND terminal is located inside the head substrate 10 is connected, according to the characteristics of the resistor is inversely proportional to the width, can greatly reduce the internal impedance of the GND wiring of the chip. In the present embodiment, since the chip size reasons, the interface 30 through the GND line connected to the metal layer 4 is located inside the end GND of the substrate 10 can be realized by the signal connections between the various modules.
[0032] Signal line interface 40 comprises a plurality of signal pins lines, each signal line average pin type arrangement, and an equal distance between two adjacent signal lines pins. In the present embodiment, a signal wire interface 40 comprises T_CL (Test Clock Pin, Test Clock) pin 41, KEY (Key Pin, key) pin 42, TEST1 (Test Pin 1, a test pin) Pin 43, SCK (serial clock, a serial clock) 44, TEST2 (test pin 2, test pin 2) pin 45, SIO (SerialData Input And Output, send and receive serial data) pin 46, TEST3 (test pin 3, test pin 3) and a pin 47 CS (chip Select oN / OFF, the chip select switch) 48 pin.
[0033]This embodiment also provides a display device including a PLED glass (not shown) and a PLD drive chip as described above. The PLED drive chip is used to drive the PLED glass and convert the information you need to display to the drive signal required for PLED.
[0034] This embodiment enables the VDD interface 20 and the GND interface 30 on both ends of the signal line interface 40, so that the VDD interface 20 and the GND interface 30 have sufficient space to set the width of the power supply connection, reduce the impedance of the power supply connection, thereby Reduce the pressure drop on the loop, reducing the decrease in the brightness of the PLED display, while reducing the heat loss of the power supply, increasing the efficiency of the battery. By setting a plurality of VDD pins 21 and GND pin 31, the impedance of the power supply connection is further reduced. By flushing the outer VDD wiring 50, the outermost GND wiring 60 is flush with the edge of the PLED drive chip, the width dimension of the external VDD wiring 50, the outer GND connection 60 is maximized. By setting the external VDD wiring 50, the long width of the outer GND connection 60 is equal to the minimum, the impedance of the power supply is minimized. Connect the GND interface 30 and the GND end through the multilayer metal wire, depending on the characteristics of the resistance and the width, the impedance of the internal GND trace in the chip can be greatly reduced.
[0035] In the drawings, the size and relative dimensions of the layers and regions are exaggerated for clarity. It should be understood that when a component such as a layer, a region or substrate is referred to as "formed", "set" or "located" on another element, the element can be directly disposed on the other element, or also Intermediate components can be present. Conversely, when the element is referred to as "directly formed in" or "directly disposed in" another element, there is no intermediate element.
[0036] The various technical features of the above examples may perform any combination, in order to make the description, the various technical features of the above embodiments are not described, however, as long as the combination of these technical features does not have contradictions, It should be considered as the scope of this specification.
[0037] In this paper, the term "installation", "connected", "connection" will be broadly understood unless otherwise specified, and "Connect", for example, may be a fixed connection, or a detachable connection, or integrally connected; It is a mechanical connection or an electrical connection; it can be directly connected, or the intermediate medium can be indirectly connected, which can be in the interior of the two components. The specific meaning of the above terms can be understood in detail to those skilled in the art.
[0038] In this article, the term "top", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", "vertical", The orientation or positional relationship of the "horizontal" or the like is based on the orientation or positional relationship shown in the drawings, which is only the clear and convenient description of the technical solution, and is therefore uninusable to limit the invention.
[0039] Herein, the sequence adjective "first", "first", "first", "first", "first", and the like "first", and "first", which are simplified, and the components described above must be in accordance with the given order, or time, space, Levels or other restrictions.
[0040] In this article, the meaning of "multiple" and "several" is two or more unless otherwise stated.
[0041] Here, the term "comprising", "comprising" or any other variable is intended to cover non-exclusive inclusive, except for those elements listed, and other elements that are not explicitly listed.
[0042] As described above, only the specific embodiments of the present invention, but the scope of the invention is not limited thereto, and any technicress, those skilled in the art, can easily think of change or replacement within the scope of the present invention, It should be covered within the scope of the invention. Therefore, the scope of the invention should be based on the scope of protection of the claims.
