Bridging system of PCIE bus and AXI bus

Abstract

The invention discloses a bridging system of a PCIE bus and an AXI bus. The bridging system comprises a first bridging module, a second bridging module and a third bridging module. The first bridging module is used for performing read-write configuration of the User register. The second bridging module is used for converting the input data stream in the AXI format sent by the AXI bus into the PCIE format and transmitting the input data stream in the PCIE format to the PCIE bus so as to finish the conversion of the input data stream from the AXI format to the PCIE format. The third bridging module is used for converting the output data stream in the PCIE format sent by the PCIE bus into the AXI format and transmitting the AXI format to the AXI bus so as to finish the conversion of the output data stream from the PCIE format to the AXI format. According to the invention, the control complexity of the User end can be reduced, and the data transmission efficiency can be improved.

Description

technical field [0001] The invention relates to the technical field of data exchange networks, in particular to a bridging system between a PCIE bus and an AXI bus. Background technique [0002] PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion interface standard and an extension of the PCI specification. The PCIE bus was introduced by Intel Corporation in 2004. It was originally designed for high-speed audio and video data stream processing, and was later used to increase the data transfer rate from measurement devices to computer memory. Due to the high performance and high bandwidth of the PCIE bus (currently the latest GEN5 standard, the unidirectional speed of one channel can reach 32Gbit / s, and there is still considerable development potential, while PCIE supports x1, x2, x4, x8, x16, x32 The multi-channel mode is very scalable and can meet the different requirements of different system devices for data transmission bandwidth),...

AI Technical Summary

Problems solved by technology

During data transmission in this solution, all PCIE information is packaged on the AXI4-Stream data bus and sent to the User side. The User judges whether to configure the read-write information or the data stream according to the type of the TLP packet, which will reduce the efficiency of the DMA. , and it will also increase the difficulty of unpacking and grouping on the User side

In addition, due to the single-channel transmission, the user side needs to buffer the received data packets and the data packets to be sent first, and then transmit them one by one after scheduling, which is more complicated for the user side to control, and the transmission efficiency is low

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