An ultra-low temperature wafer implantation platform

Abstract

The invention provides an ultra-low temperature wafer injection platform. The ultra-low temperature wafer injection platform at least includes a front-end wafer transfer module, a loading module, a vacuum transfer module, a vacuum cooling module, a vacuum injection module, and a vacuum heating module. The front modules cooperate with each other and form a An organic whole; this organic whole realizes ultra-low temperature wafer ion implantation; in the vacuum cooling module, the wafer is cooled rapidly through the cooling platform for cooling the wafer and the electrostatic chuck for absorbing the wafer, so that the wafer is in an ultra-low temperature state, and the ultra-low temperature The temperature in the state is below minus 50 degrees Celsius. The present invention effectively suppresses the dynamic annealing in the ion implantation process, so that the interstitial position atoms can no longer return to the replacement position of the lattice, so that the number of amorphous packets increases and the range of amorphous packets gradually expands. Finally, the boundaries of all amorphous packets are connected at Form a complete amorphous layer together; the invention realizes ultra-low temperature ion implantation and forms a complete amorphous layer.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and processing, and relates to an ultra-low temperature wafer implantation platform, which is suitable for ion implantation equipment. Background technique [0002] Semiconductor devices have been developing toward miniaturization for a long time. According to Moore's Law, the number of semiconductor devices integrated on a unit area of ​​an integrated circuit chip will double every 18 months, and with the miniaturization of semiconductor devices , Most of the internal structures of semiconductor devices are bound to be scaled down proportionally. At present, the critical dimensions of semiconductor devices have reached the nanometer or deep nanometer level. How to manufacture ultra-shallow junctions and abrupt junctions in semiconductor devices, and how to more completely repair ion implantation end-of-range defects (EOR Damage) in the manufacturing process of semiconductor devices have...

AI Technical Summary

Problems solved by technology

Because of the dynamic annealing phenomenon during normal temperature ion implantation or shallow low temperature ion implantation, normal temperature ion implantation or shallow low temperature ion implantation cannot form the required amorphous layer on the wafer surface well.

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